Method for integration of interpretation and translation in a microprocessor

1. A method comprising:

interpreting, a plurality of times, target instructions included in a sequence of target instructions designed for execution on a target processor for execution by a host processor different than said target processor;

collecting statistics regarding execution of instructions in the sequence of target instructions as the sequence is interpreted;

using the statistics to determine whether to cease interpreting the target instructions;

translating into host instructions the target instructions included in the sequence of target instructions after ceasing said interpreting to produce translated host instructions; and

executing the translated host instructions by said host processor in response to a determination that the sequence of target instructions is to be executed.

2. The method of claim 1 , wherein the statistics comprise a measure of a number of times the sequence of target instructions have executed, and wherein the method further comprises storing the translated host instructions.

3. The method of claim 1 , wherein the statistics comprise an address of an instruction to which a target instruction including a branch operation branches, and wherein the method further comprises storing the translated host instructions.

4. The method of claim 1 , wherein the statistics comprise a measure of a likelihood of a branch being taken, and wherein the method further comprises storing the translated host instructions.

5. A system comprising:

an interpreter configured to interpret a target instruction included in a plurality of target instructions designed for execution on a target processor, wherein said interpreted target instruction is executable by a host processor different than said target processor, wherein the interpreter is further configured to track a number of times a sequence of instructions including said interpreted target instruction is executed by said host processor; and

a translator configured to translate said sequence of instructions to produce translated instructions executable by said host processor and then store the translated instructions.

6. The system of claim 5 , wherein the translator is further configured to optimize and link the sequence of instructions, and wherein the system further comprises a storage device configured to store translated instructions.

7. The system of claim 5 , wherein the translator is further configured to translate a sequence of instructions after the sequence has been executed a predetermined number of times, and wherein the system further comprises a storage device configured to store translated instructions.

8. The system of claim 5 , wherein the translator is further configured to translate a sequence of instructions after the sequence has been executed a predetermined number of times without generating an exception, and wherein the system further comprises a storage device configured to store translated instructions.

9. The system of claim 5 , wherein the interpreter is further configured to record a number of times a particular branch instruction is executed.

10. The system of claim 5 , wherein the interpreter is further configured to determine a measure of a likelihood of a particular branch operation taking place.

11. The system of claim 5 , wherein the interpreter is further configured to speculatively determine a sequence of instructions to be a super-block after being executed a number of times.

12. The system of claim 5 , wherein the interpreter is further configured to bring a state of a target processor up-to-date as target instructions are interpreted and executed.

13. A method for executing a plurality of instructions for a target processor by using a host processor, wherein the host processor and the target processor have different instruction sets, the method comprising:

interpreting a plurality of target instructions designed for a target processor, wherein interpreted instructions are executable by a host processor different than said target processor;

storing information including a number of times an instruction is executed by said host processor; and

translating a sequence of instructions into host instructions executable by said host processor from the plurality of target instructions provided that a number of times the sequence of instructions has been executed exceeds a preset count.

14. The method of claim 13 , wherein said translating comprises optimizing the sequence of target instructions.

15. The method of claim 13 , wherein said translating comprises linking the sequence of target instructions.

16. The method of claim 13 , further comprising:

rolling back to a last known correct target state upon detecting an exception.

17. The method of claim 16 , further comprising:

interpreting target instructions sequentially to a point of exception; and

handling the exception.

18. A tangible computer-readable medium having instructions stored thereon, the instructions comprising:

instructions to interpret, a plurality of times, target instructions included in a sequence of target instructions designed for execution on a target processor for execution by a host processor having an instruction set different than that of the target processor;

instructions to collect statistics regarding execution of instructions in the sequence of target instructions as the sequence is interpreted;

instructions to use the statistics to determine whether to cease interpreting the target instructions;

instructions to translate into host instructions target instructions included in the sequence of target instructions after ceasing said interpreting to produce translated host instructions; and

instructions to execute the translated host instructions by said host processor in response to a determination that the sequence of target instructions is to be executed.

19. The computer-readable medium as claimed in claim 18 , wherein the statistics comprise a measure of a number of times the sequence of target instructions have executed, and wherein the system further comprises means for storing the translated host instructions.

20. The computer-readable medium as claimed in claim 18 , wherein the statistics comprise an address of an instruction to which a target instruction including a branch operation branches, and wherein the system further comprises means for storing the translated host instructions.

21. The computer-readable medium as claimed in claim 18 , wherein the statistics comprise a measure of a likelihood of a branch being taken, and wherein the system further comprises means for storing the translated host instructions.