Method and system for using external storage to amortize CPU cycle utilization
View Patent ↗A method and system for using external storage to amortize CPU cycle utilization, wherein translated instructions are stored in a storage medium and subsequently accessed on a subsequent execution of a non-native application in order to amortize CPU cycles used in generating the translated instructions.
1. A computing device, comprising:
a processor; and
a memory location external to the processor, wherein the memory location is operable to store a plurality of translated instructions,
wherein the processor is operable to access the translated instructions from the memory location external to the processor responsive to a context switch, and wherein the processor is operable to execute the translated instructions responsive to accessing the memory location external to the processor.
2. The computing device of claim 1 , further comprising:
a cache memory including the memory location external to the processor.
3. The computing device of claim 1 , further comprising:
a system memory including the memory location external to the processor.
4. The computing device of claim 1 , further comprising:
a disk storage including the memory location external to the processor.
5. The computing device of claim 1 , wherein the translated instructions include pipeline instructions for the processor.
6. The computing device of claim 5 , wherein the pipeline instructions comprise very long instruction word (VLIW) instructions.
7. The computing device of claim 1 , wherein the translated instructions include a micro-architecture state of the processor.
8. The computing device of claim 1 , wherein the translated instructions include branch prediction information.
9. The computing device of claim 1 , further comprising:
an instruction decoder operable to generate the translated instructions.
10. A computing device, comprising:
a processor environment; and
a memory location external to the processor environment, wherein the memory location is operable to store a plurality of translated instructions,
wherein the processor environment is operable to access the translated instructions from the memory location external to the processor environment responsive to a context switch, and wherein the processor environment is operable to execute the translated instructions responsive to accessing the memory location external to the processor environment.
11. The computing device of claim 10 , wherein the processor environment comprises a processor.
12. The computing device of claim 10 , further comprising:
a system memory including the memory location external to the processor environment.
13. The computing device of claim 10 , further comprising:
a disk storage including the memory location external to the processor environment.
14. The computing device of claim 10 , wherein the translated instructions include pipeline instructions for the processor environment.
15. The computing device of claim 14 , wherein the pipeline instructions comprise very long instruction word (VLIW) instructions.
16. A computing device, comprising:
a processor; and
a memory location external to the processor, wherein the memory location is operable to store a plurality of translated instructions that are generated during a first time period,
wherein subsequent to the first time period, the processor is operable to access the translated instructions from the memory location external to the processor responsive to a context switch, and wherein the processor is operable to execute the translated instructions responsive to accessing the memory location external to the processor.
17. The computing device of claim 16 , further comprising:
a system memory including the memory location external to the processor.
18. The computing device of claim 16 , further comprising:
a disk storage including the memory location external to the processor.
19. The computing device of claim 16 , wherein the translated instructions include pipeline instructions for the processor.
20. The computing device of claim 19 , wherein the pipeline instructions comprise very long instruction word (VLIW) instructions.