Sub-surface region with diagonal gap regions
View Patent ↗Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
1. A semiconductor device comprising:
a surface;
a plurality of surface wells of a first conductivity formed below the surface; and
a sub-surface layer of the first conductivity formed below the surface wells and electrically coupled to the surface wells, wherein the sub-surface layer comprises gap regions oriented diagonally with respect to an orientation of the surface wells.
2. The semiconductor device of claim 1 , wherein the sub-surface layer has an N-type doping.
3. The semiconductor device of claim 2 , wherein the surface wells have an N-type doping.
4. The semiconductor device of claim 3 , wherein each surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).
5. The semiconductor device of claim 1 , wherein the sub-surface layer has a P-type doping.
6. The semiconductor device of claim 5 , wherein the surface wells have a P-type doping.
7. The semiconductor device of claim 6 , wherein each surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).
8. A semiconductor device comprising:
a surface;
a first surface well of a first conductivity formed below the surface;
a second surface well of the first conductivity formed below the surface;
a region of a second conductivity below the surface and between the first surface well and the second surface well; and
a sub-surface layer of the first conductivity formed below the first and second surface wells and below the region and electrically coupled to the first and second surface wells, wherein the sub-surface layer comprises gap regions oriented diagonally with respect to an orientation of the first and second surface wells without isolating the region.
9. The semiconductor device of claim 8 , wherein the sub-surface layer has an N-type doping.
10. The semiconductor device of claim 9 , wherein the surface wells have an N-type doping and wherein the region has a P-type doping.
11. The semiconductor device of claim 10 , wherein each surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).
12. The semiconductor device of claim 8 , wherein the sub-surface layer has a P-type doping.
13. The semiconductor device of claim 12 , wherein the surface wells have a P-type doping and wherein the region has a N-type doping.
14. The semiconductor device of claim 13 , wherein each surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).
15. A semiconductor device comprising:
a surface;
a first surface well of a first conductivity formed below the surface;
a second surface well of the first conductivity formed below the surface; and
a sub-surface mesh structure of the first conductivity formed below the first and second surface wells and electrically coupled to the first and second surface wells, wherein the sub-surface mesh structure is oriented diagonally with respect to an orientation of the first and second surface wells.
16. The semiconductor device of claim 15 , wherein the sub-surface mesh structure has an N-type doping.
17. The semiconductor device of claim 16 , wherein the surface wells have an N-type doping.
18. The semiconductor device of claim 17 , wherein each surface well includes a p-type MOSFET (metal oxide semiconductor field effect transistor).
19. The semiconductor device of claim 15 , wherein the sub-surface mesh structure has a P-type doping.
20. The semiconductor device of claim 19 , wherein the surface wells have a P-type doping, and
wherein each surface well includes an n-type MOSFET (metal oxide semiconductor field effect transistor).