Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine
View Patent ↗A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.
1. A method, comprising:
using a first bit of an entry of a translation look aside buffer (TLB) and a second bit, which is unavailable in the entry, to perform a logical operation;
storing a result of the logical operation in the entry; and
permitting access to the entry based on the result.
2. The method of claim 1 , wherein said permitting comprises:
allowing a virtual machine context to access the entry based on the result.
3. The method of claim 2 , further comprising:
obtaining the second bit from the virtual machine context.
4. The method of claim 1 , wherein at least one of the first and second bits is a dirty bit.
5. The method of claim 1 , wherein at least one of the first and second bits is a read/write bit.
6. The method of claim 1 , wherein the logical operation is a logical AND operation.
7. The method of claim 1 , further comprising:
storing entries for a virtual machine context in the TLB; and
storing entries for a host machine context in the TLB.
8. An apparatus, comprising:
means for using a first bit of an entry of a translation look aside buffer (TLB) and a second bit, which is unavailable in the entry, to perform a logical operation;
means for storing a result of the logical operation in the entry; and
means for permitting access to the entry based on the result.
9. The apparatus of claim 8 , wherein the means for permitting comprises:
means for allowing a virtual machine context to access the entry based on the result.
10. The apparatus of claim 9 , further comprising:
means for obtaining the second bit from the virtual machine context.
11. The apparatus of claim 8 , wherein at least one of the first and second bits is a dirty bit.
12. The apparatus of claim 8 , wherein at least one of the first and second bits is a read/write bit.
13. The apparatus of claim 8 , wherein the logical operation is a logical AND operation.
14. The apparatus of claim 8 , further comprising:
means for storing entries for a virtual machine context in the TLB; and
means for storing entries for a host machine context in the TLB.
15. A method, comprising:
enabling a memory protection signal for a translation look aside buffer (TLB);
responsive to assertion of a memory operation signal for an entry of the TLB, performing a first logical operation involving a first bit from the entry to determine a first result and performing a second logical operation involving a second bit from the entry to determine a second result; and
if at least one of the first and second results indicates a violation of memory protection for the TLB, signaling occurrence of the violation.
16. The method of claim 15 , wherein said performing the first logical operation comprises:
performing a logical AND operation with the memory protection signal, the memory operation signal, and the first bit from the entry.
17. The method of claim 15 , wherein said performing the second logical operation comprises:
performing a logical AND operation with the memory operation signal and the second bit from the entry.
18. The method of claim 15 , wherein the first bit comprises a read/write bit.
19. The method of claim 15 , wherein the second bit comprises a dirty bit.
20. The method of claim 15 , further comprising:
storing entries for a virtual machine context in the TLB; and
storing entries for a host machine context in the TLB.