Secure memory access system and method
View Patent ↗A secure memory access system and method for providing secure access to Hyper Management Mode memory ranges is presented.
1. An apparatus comprising:
a memory operable to store memory configuration information; and
a processor operable to perform a security enhancing operation on the memory configuration information in response to switching from a first processor operating mode to a second processor operating mode.
2. The apparatus of claim 1 , wherein the memory comprises memory type range registers (MTRRs).
3. The apparatus of claim 1 , wherein the memory comprises a programmable attribute table (PAT).
4. The apparatus of claim 1 , wherein the processor is further operable to move the memory configuration information from a first memory location to a second memory location.
5. The apparatus of claim 4 , wherein the processor is further operable to change the memory configuration information at the first memory location.
6. The apparatus of claim 4 , wherein the processor is further operable to perform a second security enhancing operation on the memory configuration information in response to switching from the second processor operating mode to the first processor operating mode.
7. The apparatus of claim 6 , wherein the processor is further operable to move the memory configuration information from the second memory location to the first memory location.
8. The apparatus of claim 1 , wherein the second processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.
9. An apparatus comprising:
a first memory location operable to store memory configuration information;
a second memory location; and
a processor operable to perform a security enhancing operation on the memory configuration information by using the first memory location and the second memory location in response to switching into a pre-defined processor operating mode, wherein the memory configuration information is associated with the pre-defined processor operating mode.
10. The apparatus of claim 9 , wherein the first memory location is included in memory type range registers (MTRRs).
11. The apparatus of claim 9 , wherein the first memory location is included in a programmable attribute table (PAT).
12. The apparatus of claim 9 , wherein the processor is further operable to move the memory configuration information from the first memory location to the second memory location.
13. The apparatus of claim 12 , wherein the processor is further operable to change the memory configuration information at the first memory location.
14. The apparatus of claim 12 , wherein the processor is further operable to perform a second security enhancing operation on the memory configuration information in response to switching out of the pre-defined processor operating mode, and wherein the processor is further operable to move the memory configuration information from the second memory location to the first memory location.
15. The apparatus of claim 9 , wherein the pre-defined processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.
16. An apparatus comprising:
circuitry configured to detect a mode-triggering event; and
a processor configured to switch from a first processor operating mode to a second processor operating mode if the mode triggering event is detected, wherein the processor is further configured to perform a security enhancing operation on memory configuration information associated with the second processor operating mode.
17. The apparatus of claim 16 , wherein the processor is further configured to move the memory configuration information from a first memory location to a second memory location.
18. The apparatus of claim 17 , wherein the processor is further configured to change the memory configuration information at the first memory location.
19. The apparatus of claim 17 , wherein the processor is further configured to perform a second security enhancing operation on the memory configuration information in response to switching from the second processor operating mode to the first processor operating mode, and wherein the processor is further configured to move the memory configuration information from the second memory location to the first memory location.
20. The apparatus of claim 16 , wherein the second processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.