System and method for reducing temperature variation during burn in
View Patent ↗Systems and methods for reducing temperature variation during burn-in testing. In one embodiment, power consumed by an integrated circuit under test is measured. An ambient temperature associated with the integrated circuit is measured. A desired junction temperature of the integrated circuit is achieved by adjusting a body bias voltage of the integrated circuit. By controlling temperature of individual integrated circuits, temperature variation during burn-in testing can be reduced.
1. A method comprising:
applying a range of body bias voltage values to a first integrated circuit to reduce a leakage current of the first integrated circuit to an acceptable value, wherein the first integrated circuit includes a plurality of devices;
responsive to the leakage current of the first integrated circuit decreasing to the acceptable value, identifying a body bias voltage value applied to the first integrated circuit by the applying the range of body bias voltage values; and
performing burn-in testing of a second integrated circuit, wherein said performing burn-in testing includes:
applying the body bias voltage value to the second integrated circuit; and
adjusting the body bias voltage value to obtain an acceptable junction temperature for the second integrated circuit in response to a calculation that involves a power measurement, an ambient temperature measurement, and a thermal resistance value.
2. The method of claim 1 , further comprising:
storing the body bias voltage value.
3. The method of claim 1 , wherein the first integrated circuit is unpackaged.
4. The method of claim 1 , wherein the second integrated circuit is part of a batch of integrated circuits.
5. The method of claim 4 , wherein the batch of integrated circuits comprises a wafer of integrated circuits.
6. The method of claim 1 , wherein said applying and said identifying are performed during wafer testing.
7. The method of claim 1 , wherein the plurality of devices comprise p-type MOSFET (pFET) devices and n-type MOSFET (nFET) devices.
8. A method comprising:
by applying a range of body bias voltage values to a first integrated circuit, determining a plurality of body bias voltage values that cause a leakage current of the first integrated circuit to decrease to an acceptable value, wherein the first integrated circuit includes a plurality of devices; and
performing burn-in testing of a second integrated circuit, wherein said performing burn-in testing includes:
applying the plurality of body bias voltage values to the second integrated circuit; and
adjusting the plurality of body bias voltage values to obtain an acceptable junction temperature for the second integrated circuit in response to a calculation that involves a power measurement, an ambient temperature measurement, and a thermal resistance value.
9. The method of claim 8 , further comprising:
storing the plurality of body bias voltage values.
10. The method of claim 8 , wherein the first integrated circuit is unpackaged.
11. The method of claim 8 , further comprising:
performing burn-in testing of a group of integrated circuits by applying the plurality of body bias voltage values to the group of integrated circuits.
12. The method of claim 11 , wherein the group of integrated circuits comprises a batch of integrated circuits.
13. The method of claim 12 , wherein the batch of integrated circuits comprises a wafer of integrated circuits.
14. The method of claim 8 , wherein said determining is performed during wafer testing.
15. The method of claim 8 , wherein the plurality of devices comprise p-type MOSFET (pFET) devices and n-type MOSFET (nFET) devices.
16. A method comprising:
by applying a range of body bias voltage values to a first integrated circuit, testing the first integrated circuit to determine a set of body bias voltage values that cause a leakage current of the first integrated circuit to decrease to an acceptable value, wherein the first integrated circuit includes a plurality of devices;
storing the set of body bias voltage values; and
performing burn-in testing of a second integrated circuit, wherein said performing burn-in testing includes:
accessing the set of body bias voltage values;
applying the set of body bias voltage values to the second integrated circuit; and
adjusting the set of body bias voltage values to obtain an acceptable junction temperature for the second integrated circuit in response to a calculation that involves a power measurement, an ambient temperature measurement, and a thermal resistance value.
17. The method of claim 16 , wherein the first integrated circuit is unpackaged.
18. The method of claim 16 , wherein the second integrated circuit is part of a batch of integrated circuits.
19. The method of claim 18 , wherein the batch of integrated circuits comprises a wafer of integrated circuits.
20. The method of claim 16 , wherein said testing is performed during wafer testing, and wherein the plurality of devices comprise p-type MOSFET (pFET) devices and n-type MOSFET (nFET) devices.