Systems and methods for voltage distribution via multiple epitaxial layers
View Patent ↗Systems and methods for voltage distribution via multiple epitaxial layers. In accordance with a first embodiment of the present invention, an integrated circuit comprises a wafer substrate of a connectivity type. A first epitaxial layer of a connectivity type is disposed upon a second epitaxial layer of an opposite connectivity type, which is disposed upon the wafer substrate.
1. An integrated circuit comprising:
a wafer substrate of a conductivity type;
a first epitaxial layer of a conductivity type disposed upon
a second epitaxial layer of an opposite conductivity type disposed upon said wafer; and
a deep well of said conductivity type for coupling a body biasing voltage from said wafer substrate to body terminals of field effect transistors formed in said first epitaxial layer.
2. The integrated circuit of claim 1 further comprising a via structure formed in a hole of said second epitaxial layer wherein said body biasing voltage is coupled from said wafer substrate to said first epitaxial layer by means of said via structure.
3. The integrated circuit of claim 2 wherein said body biasing voltage is conducted substantially laterally within said wafer substrate.
4. The integrated circuit of claim 1 wherein said layer of an opposite conductivity couples a body biasing voltage to body terminals of a field effect transistor formed in a well of said opposite conductivity type.
5. The integrated circuit of claim 4 wherein said body biasing voltage is conducted substantially laterally within said layer of an opposite conductivity.
6. The integrated circuit of claim 4 further comprising a deep well of said opposite conductivity type wherein said body biasing voltage is coupled from said second epitaxial layer to said well via said deep well.
7. The integrated circuit of claim 1 further comprising a tap of said opposite conductivity type formed in a well of said opposite conductivity type for coupling a voltage to said second epitaxial layer.
8. The integrated circuit of claim 1 further comprising a tap of said conductivity type formed in said second epitaxial layer for coupling a voltage to said wafer substrate.
9. An integrated circuit comprising:
a first epitaxial layer of a conduction type for conducting a first voltage substantially parallel to a plane of said first epitaxial layer;
a second epitaxial layer of opposite conduction type underlying said first epitaxial layer for conducting a second voltage substantially parallel to a plane of said second epitaxial layer; and
complementary metal oxide semiconductor devices disposed in said first epitaxial layer.
10. The integrated circuit of claim 9 wherein said first voltage is a body biasing voltage for a field effect transistor formed in said first epitaxial layer.
11. The integrated circuit of claim 10 further comprising a tap in said first epitaxial layer for coupling said body biasing voltage to said first epitaxial layer.
12. The integrated circuit of claim 9 comprising a well of said opposite conduction type within said first epitaxial layer for forming a field effect transistor.
13. The integrated circuit of claim 12 comprising a deep structure of said opposite conduction type for coupling said well to said second epitaxial layer.
14. The integrated circuit of claim 13 wherein conduction through said deep structure is substantially perpendicular to said plane of said first epitaxial layer.
15. The integrated circuit of claim 13 wherein said deep structure is for coupling a body biasing voltage from said second epitaxial layer to said well.