Power efficient multiplexer

1. A power efficient multiplexer comprising:

a transmission gate structure for selectively passing one of a plurality of input signals; and

a stacked inverter circuit for inverting said one of a plurality of input signals at an output node, wherein said one of a plurality of input signals controls all devices of said stacked inverter circuit.

2. The power efficient multiplexer of claim 1 wherein said transmission gate structure comprises two transmission gates.

3. The power efficient multiplexer of claim 2 wherein one bit and the complement of said one bit determine said passing of one of a plurality of input signals.

4. The power efficient multiplexer of claim 2 wherein said stacked inverter circuit comprises:

a first plurality of devices of a first type coupled in series;

a second plurality of devices of a second type coupled in series, said second type opposite to said first type; and

wherein said first and said second pluralities of devices are coupled in series.

5. The power efficient multiplexer of claim 4 wherein said first plurality of devices comprises two devices.

6. The power efficient multiplexer of claim 4 wherein said second plurality of devices of said second type comprises three n-type devices.

7. The power efficient multiplexer of claim 4 wherein said stacked inverter circuit is characterized in having a greater switching time duration than an inversion performed by an inverter comprising only two active devices.

8. The power efficient multiplexer of claim 4 wherein said stacked inverter circuit is characterized in having less leakage current than an inverter comprising only two active devices.

9. A method of selecting one electronic signal from a plurality of electronic signals comprising:

accessing said plurality of electronic signals;

configuring a plurality of transmission gates to select one electronic signal from said plurality of electronic signals; and

inverting said one electronic signal utilizing a stacked inverter circuit, wherein said one electronic signal controls all devices of said stacked inverter circuit.

10. The method of claim 9 wherein said configuring comprises coupling a bit value and the complement of said bit value to said plurality of transmission gates.

11. The method of claim 9 wherein said stacked inverter circuit comprises at least two p-type devices coupled in series with at least two n-type devices.

12. The method of claim 11 wherein said stacked inverter circuit is characterized in having a greater switching time duration than an inversion performed by an inverter comprising only two active devices.

13. The method of claim 11 wherein said stacked inverter circuit is characterized in having less leakage current than an inverter comprising only two active devices.

14. The method of claim 9 wherein said stacked inverter circuit comprises:

a first plurality of devices of a first type coupled in series;

a second plurality of devices of a second type coupled in series, wherein said second type is opposite to said first type; and

wherein said first and said second pluralities of devices are coupled in series and comprise at least five active devices.

15. An electronic circuit comprising:

a stacked inverter circuit comprising:

at least two devices of a first type coupled in series, coupled in series to

at least two devices of a second type coupled in series, wherein said second type is opposite to said first type;

wherein gates of each device comprising said stacked inverter circuit are coupled together;

a first conductance terminal of a first transmission gate coupled to a first electronic signal;

a first conductance terminal of a second transmission gate coupled to a second electronic signal;

second conductance terminals of said first and second transmission gates coupled to an input of said stacked inverter circuit;

wherein a first control terminal of a semiconductor type of said first transmission gate is coupled to a second control terminal of opposite semiconductor type of said second transmission gate; and

wherein a second control terminal of said opposite semiconductor type of said first transmission gate is coupled to a first control terminal of said semiconductor type of said second transmission gate.

16. The electronic circuit of claim 15 wherein said stacked inverter circuit comprises two p-type devices.

17. The electronic circuit of claim 15 wherein said stacked inverter circuit comprises three n-type devices.

18. The electronic circuit of claim 15 further comprising a latch circuit, wherein a bit value of said latch circuit is coupled to said first control terminal of a semiconductor type of said first transmission gate, and the complement of said bit value is coupled to said second control terminal of said opposite semiconductor type of said first transmission gate.