Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine
View Patent ↗A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.
1. A method, comprising:
executing a host machine application within a host machine context;
executing a virtual machine application within a virtual machine context;
storing a plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context within a physical TLB, wherein the TLB entries include a plurality of memory protection bits; and
controlling access from the virtual machine context to a TLB entry of the physical TLB, wherein said controlling access includes:
performing a logical operation with first and second memory protection bits of the TLB entry and a memory protection bit, which is unavailable in the TLB entry, from the virtual machine context to determine a result; and
storing the result in the TLB entry and permitting access to the TLB entry based on the result.
2. The method of claim 1 , wherein at least one of the first and second memory protection bits is a dirty bit.
3. The method of claim 1 , wherein at least one of the first and second memory protection bits is a read/write bit.
4. The method of claim 1 , wherein the logical operation is a logical AND operation.
5. The method of claim 1 , wherein the host machine application is a host machine operating system that executes within the host machine context and the virtual machine application is a virtual machine operating system that executes within the virtual machine context.
6. The method of claim 1 , wherein the TLB entries include respective context identifiers enabling the TLB entries to provide physical address translation for virtual addresses from both the host machine context and the virtual machine context.
7. The method of claim 1 further comprising:
updating the physical TLB with new entries if a virtual machine TLB miss occurs or a host machine TLB miss occurs, wherein the controlling access enforces memory protection on the virtual machine application.
8. A system, comprising:
a processor architecture including micro architecture code configured to execute on a CPU hardware unit of the processor architecture; and
an address translation cache for implementing a physical translation look aside buffer, wherein memory stores instructions of the micro architecture code cause the system to perform operations for memory protection, wherein the memory stores instructions comprise:
instructions to execute a host machine application within a host machine context;
instructions to execute a virtual machine application within a virtual machine context;
instructions to store a plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context within the physical TLB, wherein the TLB entries include a plurality of memory protection bits; and
instructions to control access from the virtual machine context to a TLB entry of the physical TLB, wherein the instructions to control access comprise:
instructions to perform a logical operation with first and second memory protection bits of the TLB entry and a memory protection bit, which is unavailable in the TLB entry, from the virtual machine context to determine a result; and
instructions to store the result in the TLB entry and to permit access to the TLB entry based on the result.
9. The system of claim 8 , wherein at least one of the first and second memory protection bits is a dirty bit.
10. The system of claim 8 , wherein at least one of the first and second memory protection bits is a read/write bit.
11. The system of claim 8 , wherein the logical operation is a logical AND operation.
12. The system of claim 8 , wherein the host machine application is a host machine operating system that executes within the host machine context and the virtual machine application is a virtual machine operating system that executes within the virtual machine context.
13. The system of claim 8 , wherein the TLB entries include respective context identifiers enabling the TLB entries to provide physical address translation for virtual addresses from both the host machine context and the virtual machine context.
14. The system of claim 8 , wherein the memory stores instructions further comprise:
instructions to update the physical TLB with new entries if a virtual machine TLB miss occurs or a host machine TLB miss occurs.
15. A computer readable storage device comprising computer readable code stored therein, the computer readable code comprising:
computer readable code to execute a host machine application within a host machine context;
computer readable code to execute a virtual machine application within a virtual machine context;
computer readable code to store a plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context within a physical TLB, wherein the TLB entries include a plurality of memory protection bits; and
computer readable code to control access from the virtual machine context to a TLB entry of the physical TLB, wherein the computer readable code to control access comprises:
computer readable code to perform a logical operation with first and second memory protection bits of the TLB entry and a memory protection bit, which is unavailable in the TLB entry, from the virtual machine context to determine a result; and
computer readable code to store the result in the TLB entry and to permit access to the TLB entry based on the result.
16. The computer readable storage device of claim 15 , wherein at least one of the first and second memory protection bits is a dirty bit.
17. The computer readable storage device of claim 15 , wherein at least one of the first and second memory protection bits is a read/write bit.
18. The computer readable storage device of claim 15 , wherein the logical operation is a logical AND operation.
19. The computer readable storage device of claim 15 , wherein the host machine application is a host machine operating system that executes within the host machine context and the virtual machine application is a virtual machine operating system that executes within the virtual machine context.
20. The computer readable storage device of claim 15 , wherein the TLB entries include respective context identifiers enabling the TLB entries to provide physical address translation for virtual addresses from both the host machine context and the virtual machine context.
21. The computer readable storage device of claim 15 , wherein the computer readable code further comprises:
computer readable code to update the physical TLB with new entries if a virtual machine TLB miss occurs or a host machine TLB miss occurs.