Method for generating a deep N-well pattern for an integrated circuit design
View Patent ↗A method for the design and layout for a patterned deep N-well. A Tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.
1. A method of generating a deep N-well pattern for an integrated circuit design, said method comprising:
specifying a tile comprising a first layer wherein said first layer comprises a first layer element for a deep N-well pattern;
arranging multiple instances of said tile to create a tile array covering a portion of said integrated circuit design; and
merging said tiles to produce a deep N-well pattern.
2. The method of claim 1 , wherein said tile further comprises a second layer, wherein said second layer comprises a second layer element.
3. The method of claim 2 , wherein said first layer element is identical in shape to said second layer element.
4. The method of claim 3 , wherein said first layer element is disposed rotated with respect to said second layer element.
5. The method of claim 1 , further comprising editing said tile array.
6. The method of claim 2 , further comprising flattening said first layer and said second layer.
7. A method of generating a deep N-well pattern for an integrated circuit design, said method comprising:
specifying a tile comprising a first layer wherein said first layer comprises a first layer element for a deep N-well pattern;
arranging multiple instances of said tile to create a tile array covering a portion of said integrated circuit design; and
merging said multiple instances of said tiles to produce a deep N-well pattern, wherein said deep N-well pattern is operable to provide body-bias voltage connections within said integrated circuit design.
8. The method of claim 7 , wherein said tile further comprises a second layer, wherein said second layer comprises a second layer element.
9. The method of claim 8 , wherein said first layer element is identical in shape to said second layer element.
10. The method of claim 9 , wherein said first layer element is disposed rotated with respect to said second layer element.
11. The method of claim 7 , further comprising editing said tile array.
12. The method of claim 8 , further comprising flattening said first layer and said second layer.
13. A method of generating a deep N-well pattern for an integrated circuit design, said method comprising:
specifying a tile means comprising a first layer wherein said first layer comprises a first layer element for a deep N-well pattern;
arranging multiple instances of said tile means to create a tile array means covering a portion of said integrated circuit design; and
merging said multiple instances of said tile means to produce a deep N-well pattern, wherein said deep N-well pattern is operable to provide body-bias voltage connections within said integrated circuit design.
14. The method of claim 13 , wherein said tile means further comprises a second layer, wherein said second layer comprises a second layer element.
15. The method of claim 14 , wherein said first layer element is identical in shape to said second layer element.
16. The method of claim 15 , wherein said first layer element is disposed rotated with respect to said second layer element.
17. The method of claim 13 , further comprising editing said tile array.
18. The method of claim 14 , further comprising flattening said first layer and said second layer.