Method and system for automated schematic diagram conversion to support semiconductor body bias designs

1. A computer implemented method for converting schematic diagrams, comprising:

accessing a first set of schematic diagrams, the schematic diagrams representing an integrated circuit design to be realized in physical form;

converting a plurality of a first type of circuit elements in the first set into a second type of circuit elements, the conversion automatically implemented in accordance with a set of conversion rules, and wherein said converting comprises schematically changing the number of terminals of said first type of circuit elements, and wherein said second type of circuit elements are of a type of said plurality of first type of circuit elements but represented with a different number of terminals; and

outputting a second set of schematic diagrams representing the integrated circuit design and including the second type of circuit elements, wherein said second set of schematic diagrams are operable to be stored by a memory component.

2. The method of claim 1 , further comprising:

performing a verification process on the second set, wherein at least one of the first type of circuit elements is converted into the second type of circuit element during the verification; and

outputting a finalized set of converted schematic diagrams.

3. The method of claim 1 , wherein the first type of circuit elements are three terminal transistor elements.

4. The method of claim 1 , wherein the second type of circuit elements are four terminal transistor elements.

5. The method of claim 4 , wherein the four terminal transistor elements include a body bias terminal.

6. The method of claim 1 , wherein the second set of schematic diagrams is configured to enable a body bias version of the integrated circuit design.

7. The method of claim 1 , wherein said plurality of first type of circuit elements are a P-type transistor (PFET) represented with three terminals, and wherein said second type of circuit elements are said PFET transistor represented as a PFET with four terminals, wherein a fourth terminal of said PFET transistor couples a its bulk node to N-well bias.

8. A computer system comprising a processor coupled to a bus and a memory coupled to the bus, the memory having instructions stored there in that when executed by the processor implement a method for converting schematic diagrams, comprising:

accessing a first set of schematic diagrams, the schematic diagrams representing an integrated circuit design to be realized in physical form;

converting a plurality of a first type of circuit elements in the first set into a second type of circuit elements, the conversion automatically implemented in accordance with a set of conversion rules, and wherein said converting comprises schematically changing the number of terminals of said first type of circuit elements, and wherein said second type of circuit elements are of a type of said plurality of first type of circuit elements but represented with a different number of terminals; and

outputting a second set of schematic diagrams representing the integrated circuit design and including the second type of circuit elements.

9. The system of claim 8 , further comprising:

performing a verification process on the second set, wherein at least one of the first type of circuit elements is converted into the second type of circuit element during the verification; and

outputting a finalized set of converted schematic diagrams.

10. The system of claim 8 , wherein the first type of circuit elements are three terminal transistor elements.

11. The system of claim 8 , wherein the second type of circuit elements are four terminal transistor elements.

12. The system of claim 11 , wherein the four terminal transistor elements include a body bias terminal.

13. The system of claim 8 , wherein the second set of schematic diagrams is configured to enable a body biased version of the integrated circuit design.

14. In a computer system comprising a processor coupled to a bus and a memory coupled to the bus, a computer readable memory having instructions stored there in that when executed by the processor implement a method for converting schematic diagrams, comprising:

accessing a first set of schematic diagrams, the schematic diagrams representing an integrated circuit design to be realized in physical form;

converting a plurality of a first type of circuit elements in the first set into a second type of circuit elements, the conversion automatically implemented in accordance with a set of conversion rules, and wherein said converting schematically changes the number of terminals of said first type of circuit elements, and wherein said second type of circuit elements are of a type of said plurality of first type of circuit elements but represented with a different number of terminals; and

outputting a second set of schematic diagrams representing the integrated circuit design and including the second type of circuit elements.

15. The computer readable memory of claim 14 , further comprising:

performing a verification process on the second set, wherein at least one of the first type of circuit elements is converted into the second type of circuit element during the verification; and

outputting a finalized set of converted schematic diagrams.

16. The computer readable memory of claim 14 , wherein the first type of circuit elements are three terminal transistor elements.

17. The computer readable memory of claim 14 , wherein the second type of circuit elements are four terminal transistor elements.

18. The computer readable memory of claim 17 , wherein the four terminal transistor elements include a body bias terminal.

19. The computer readable memory of claim 14 , wherein the second set of schematic diagrams is configured to enable a body biased version of the integrated circuit design.