System and method for measuring time dependent dielectric breakdown with a ring oscillator
View Patent ↗An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT) module coupled to a first ring oscillator module and a second DUT module coupled to a second ring oscillator module. A dielectric layer of the first DUT is stressed during a first mode, thereby causing time dependent dielectric breakdown in the first dielectric layer. A dielectric layer of the second DUT is maintained as a reference. The operating frequency of the first ring oscillator module, during a second mode, is a function of a gate leakage current of the stressed dielectric layer. The operating frequency of the second ring oscillator module, during the second mode, is a function of a gate leakage current the reference dielectric layer. The integrated circuit may also include a comparator module for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator modules.
1. A system for measuring time dependent dielectric breakdown comprising:
a first differential amplifier having a first input coupled to a reference voltage;
a first set of inverters coupled in series in a feedback loop between an output of said first differential amplifier and a second input of said first differential amplifier; and
a first MOSFET having a gate, a gate oxide, a source and a drain arranged in a gate—gate oxide-source/drain structure, wherein said gate oxide is subjected to time dependent dielectric breakdown during a normal operating mode and wherein said gate—gate oxide-source/drain structure is coupled as a first gate leakage current source to said second input of said first differential amplifier during a test mode.
2. The system of claim 1 , further comprising a NAND gate having a first input coupled to an enable signal and having a second input and an output coupled in series in said feedback loop.
3. The system of claim 1 , further comprising:
a second differential amplifier having a first input coupled to said reference voltage;
a second set of inverters coupled in series in a feedback loop between an output of said differential amplifier and a second input of said second differential amplifier; and
a second MOSFET having a gate, a gate oxide, a source and a drain arranged in a gate—gate oxide-source/drain structure, wherein said gate oxide is not subjected to time dependent dielectric breakdown during said normal operating mode and wherein said gate—gate oxide-source/drain structure is coupled as a second gate leakage current source to said second input of said second differential amplifier during a test mode.
4. The system of claim 3 , wherein said first MOSFET and said second MOSFET are n-channel MOSFETs.
5. The system of claim 3 , wherein said first MOSFET and said second MOSFET are p-channel MOSFETs.
6. The system of claim 3 , further comprising:
a third differential amplifier having a first input coupled to said reference voltage;
a third set of inverters coupled in series in a feedback loop between an output of said third differential amplifier and a second input of said third differential amplifier;
a third MOSFET having a gate, a gate oxide, a source and a drain arranged in a gate—gate oxide-source/drain structure, wherein said gate oxide is subjected to time dependent dielectric breakdown during said normal operating mode and wherein said gate—gate oxide-source/drain structure is coupled as a third gate leakage current source to said second input of said third differential amplifier during said test mode;
a fourth differential amplifier having a first input coupled to said reference voltage;
a fourth set of inverters coupled in series in a feedback loop between an output of said fourth differential amplifier and a second input of said fourth differential amplifier; and
a fourth MOSFET having a gate, a gate oxide, a source and a drain arranged in a gate—gate oxide-source/drain structure, wherein said gate oxide is not subjected to time dependent dielectric breakdown during said normal operating mode and wherein said gate—gate oxide-source/drain structure is coupled as a fourth gate leakage current source to said second input of said fourth differential amplifier during said test mode.
7. The system of claim 6 , wherein:
said first MOSFET and said second MOSFET are n-channel MOSFETs; and
said third MOSFET and said fourth MOSFET are p-channel MOSFETs.