Wire mesh patterns for semiconductor devices
View Patent ↗Different patterns of interconnects for connecting wells in a semiconductor device are described. For example, a semiconductor device may include n-wells and p-wells arrayed in rows and columns that lie on a rectilinear grid. Electrically conductive interconnects link at least some of the wells. The interconnects are arranged as a mesh having openings that are substantially rectangular in shape.
1. A semiconductor device comprising:
a plurality of wells comprising n-wells and p-wells arrayed in rows and columns that lie on a rectilinear grid; and
a plurality of electrically conductive interconnects linking at least some of said wells, wherein said interconnects comprise a mesh having openings that are substantially rectangular in shape.
2. The semiconductor device of claim 1 wherein said openings comprise first rectangles of a first size and second rectangles of a second size.
3. The semiconductor device of claim 2 wherein the long sides of said first rectangles are at angles of 45 degrees relative to said columns and wherein the long sides of said second rectangles are at right angles to the long sides of said first rectangles.
4. The semiconductor device of claim 1 wherein said interconnects have a uniform wire width.
5. The semiconductor device of claim 1 wherein junctions between interconnects are T-shaped at locations other than locations on the perimeter of said mesh.
6. The semiconductor device of claim 1 wherein said interconnects route body bias voltages to said wells.
7. The semiconductor device of claim 1 wherein said openings correspond to connections to p-wells.
8. A semiconductor device comprising:
a plurality of wells comprising n-wells and p-wells arrayed in rows and columns; and
a mesh of electrically conductive interconnects linking at least some of said wells, said mesh comprising parallel first interconnects diagonal to a column and parallel second interconnects perpendicular to said first interconnects, wherein a first interconnect intersects a second interconnect to form a T-shaped junction at a location other than a location on the perimeter of said mesh.
9. The semiconductor device of claim 8 wherein said first interconnects are at angles of 45 degrees relative to said columns.
10. The semiconductor device of claim 8 wherein said first interconnects are uniformly spaced a first distance apart and wherein said second interconnects are uniformly spaced a second distance apart.
11. The semiconductor device of claim 8 wherein said interconnects have a uniform wire width.
12. The semiconductor device of claim 8 wherein openings in said mesh are rectangular in shape.
13. The semiconductor device of claim 12 wherein said openings comprise a first plurality of rectangles of a first size and a second plurality of rectangles of a second size.
14. The semiconductor device of claim 12 wherein said openings correspond to connections to said p-wells.
15. The semiconductor device of claim 8 wherein said interconnects route body bias voltages to said wells.
16. A semiconductor device comprising:
a plurality of wells comprising n-wells and p-wells arrayed in rows and columns; and
a plurality of electrically conductive interconnects linking at least some of said wells, said interconnects comprising a mesh comprising a first plurality of openings having a first dimension and a second dimension and a second plurality of openings having a third dimension and a fourth dimension, said first and third dimensions oriented in a same first direction and said second and fourth dimensions oriented in a same second direction, wherein said first dimension is an integer multiple of said third dimension and said first and third dimensions are not equal, and wherein said second and fourth dimensions are relatively prime and are not equal.
17. The semiconductor device of claim 16 wherein said first direction is diagonal to said columns and said second direction is orthogonal to said first direction.
18. The semiconductor device of claim 16 wherein said first direction is at an angle of 45 degrees relative to said columns.
19. The semiconductor device of claim 16 wherein said interconnects have a uniform wire width.
20. The semiconductor device of claim 16 wherein said openings correspond to connections to said p-wells.
21. The semiconductor device of claim 16 wherein said interconnects route body bias voltages to said wells.
22. The semiconductor device of claim 16 wherein junctions between interconnects are T-shaped at locations other than locations on the perimeter of said mesh.