IP Library Granted Patent US 8,359,443
Granted Patent B2
US 8,359,443 · App. 13/165,560 · Granted Jan 22, 2013

Secure memory access system and method

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Quick Facts
Patent No.
US 8,359,443
App. No.
13/165,560
Granted
Jan 22, 2013
Kind
B2
Abstract

A secure memory access system and method for providing secure access to Hyper Management Mode memory ranges is presented.

Claims (45)

1. A computer-readable storage device comprising computer-executable instructions stored therein, the computer-executable instructions comprising:

instructions to store memory configuration information; and

instructions to perform a security enhancing operation on the memory configuration information in response to switching from a first processor operating mode to a second processor operating mode.

2. The computer-readable storage device of claim 1 , wherein the instructions to store comprise:

instructions to receive the memory configuration information at memory type range registers (MTRRs).

3. The computer-readable storage device of claim 1 , wherein the instructions to store comprise:

instructions to receive the memory configuration information at a programmable attribute table (PAT).

4. The computer-readable storage device of claim 1 , wherein the instructions to perform comprise:

instructions to move the memory configuration information from a first memory location to a second memory location.

5. The computer-readable storage device of claim 4 , wherein the instructions to perform further comprise:

instructions to change the memory configuration information at the first memory location.

6. The computer-readable storage device of claim 4 , wherein the computer-executable instructions further comprise:

instructions to perform a second security enhancing operation on the memory configuration information in response to switching from the second processor operating mode to the first processor operating mode.

7. The computer-readable storage device of claim 6 , wherein the instructions to perform the second security enhancing operation comprise:

instructions to move the memory configuration information from the second memory location to the first memory location.

8. The computer-readable storage device of claim 1 , wherein the second processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.

9. A computer-readable storage device comprising computer-executable instructions stored therein, the computer-executable instructions comprising:

instructions to store memory configuration information associated with a processor operating mode in a first memory location; and

instructions to perform a security enhancing operation on the memory configuration information by using the first memory location and a second memory location in response to switching into the processor operating mode.

10. The computer-readable storage device of claim 9 , wherein the instructions to store comprise:

instructions to receive the memory configuration information at the first memory location in memory type range registers (MTRRs).

11. The computer-readable storage device of claim 9 , wherein the instructions to store comprise:

instructions to receive the memory configuration information at the first memory location in a programmable attribute table (PAT).

12. The computer-readable storage device of claim 9 , wherein the instructions to perform comprise:

instructions to move the memory configuration information from the first memory location to the second memory location.

13. The computer-readable storage device of claim 12 , wherein the instructions to perform further comprise:

instructions to change the memory configuration information at the first memory location.

14. The computer-readable storage device of claim 12 , wherein the computer-executable instructions further comprise:

instructions to perform a second security enhancing operation on the memory configuration information in response to switching out of the processor operating mode,

wherein the instructions to perform the second security enhancing operation comprise:

instructions to move the memory configuration information from the second memory location to the first memory location.

15. The computer-readable storage device of claim 9 , wherein the processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.

16. A computer-readable storage device comprising computer-executable instructions stored therein, the computer-executable instructions comprising:

instructions to detect a mode-triggering event;

instructions to switch from a first processor operating mode to a second processor operating mode if the mode triggering event is detected; and

instructions to perform a security enhancing operation on memory configuration information associated with the second processor operating mode.

17. The computer-readable storage device of claim 16 , wherein the instructions to perform comprise:

instructions to move the memory configuration information from a first memory location to a second memory location.

18. The computer-readable storage device of claim 17 , wherein the instructions to perform further comprise:

instructions to change the memory configuration information at the first memory location.

19. The computer-readable storage device of claim 17 , wherein the computer-executable instructions further comprise:

instructions to perform a second security enhancing operation on the memory configuration information in response to switching from the second processor operating mode to the first processor operating mode,

wherein the instructions to perform the second security enhancing operation comprise:

instructions to move the memory configuration information from the second memory location to the first memory location.

20. The computer-readable storage device of claim 16 , wherein the second processor operating mode is a Hyper Management Mode, and wherein the memory configuration information includes memory type designations for memory ranges associated with the Hyper Management Mode.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 6, 2015
From: INTELLECTUAL VENTURES FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036797/0356 →
MERGER Recorded Sep 29, 2015
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036711/0160 →