Methods and systems employing a flag for deferring exception handling to a commit or rollback point

1. A method of exception handling, said method comprising:

maintaining, in a first register, first state information associated with executing a first code sequence of native instructions, said native instructions translated from non-native instructions associated with a non-native application;

in a commit operation, transferring said first state information at a commit point to a second register that is architecturally visible to said application;

in a rollback operation, transferring second state information from said second register to said first register, wherein said second state information is associated with a second code sequence that preceded said first code sequence;

identifying, during execution of any instruction in said first code sequence, an event to be handled;

setting one of two flag bits in said second register to indicate that handling of said event is to be deferred; and

generating an exception corresponding to said event whenever one of said flag bits is set, wherein said exception causes said event to be handled subsequent to said identifying, and wherein said exception is generated at the next commit operation when a first of said flag bits is set and at the next rollback operation when a second of said flag bits is set.

2. The method of claim 1 wherein said event is a trap.

3. The method of claim 1 wherein said non-native instructions comprise x86 instructions and wherein said native instructions comprise Very Long Instruction Word (VLIW) instructions.

4. The method of claim 1 further comprising:

clearing said flag bit.

5. A computer system for performing exception handling comprising:

a processor; and

memory coupled to said processor, said processor, in response to executing instructions stored in said memory, for:

maintaining, in a first register, first state information associated with executing a first code sequence of native instructions, said native instructions translated from non-native instructions associated with a non-native application;

in a commit operation, transferring said first state information at a commit point to a second register that is architecturally visible to said application;

in a rollback operation, transferring second state information from said second register to said first register, wherein said second state information is associated with a second code sequence that preceded said first code sequence;

identifying, during execution of any instruction in said first code sequence, an event to be handled;

setting one of two flag bits in said second register to indicate that handling of said event is to be deferred; and

generating an exception corresponding to said event whenever one of said flag bits is set, wherein said exception causes said event to be handled subsequent to said identifying, and wherein said exception is generated at the next commit operation when a first of said flag bits is set and at the next rollback operation when a second of said flag bits is set.

6. The computer system of claim 5 wherein said event is a trap.

7. The computer system of claim 5 wherein said non-native instructions comprise x86 instructions and wherein said native instructions comprise Very Long Instruction Word (VLIW) instructions.

8. The computer system of claim 5 wherein said method further comprises:

clearing said flag bit.

9. A method of executing a translated code sequence comprising:

executing a sequence of native instructions that were translated from a sequence of non-native instructions;

during said executing, identifying an event that is to be executed only at an architecturally precise point of execution, wherein said architecturally precise point corresponds to a point at which state information held in a first register and associated with said native instructions would be the same as state information held in a second register and associated with said non-native instructions;

in response to said identifying, setting a two-bit flag in said second register and deferring execution of said event; and

at said architecturally precise point of execution, executing said event if said flag is set, wherein said architecturally precise point corresponds to a commit operation when said flag has a first value and to a rollback operation when said flag has a second value; wherein as a result of a commit operation, state information in said first and second registers is associated with a first sequence of native instructions, and wherein as a result of a rollback operation, state information in said first and second registers is associated with a second sequence of native instructions that preceded said first sequence.

10. The method of claim 9 wherein said executing said event comprises:

in response to said flag being set, generating an exception when said architecturally precise point of execution has been reached.

11. The method of claim 10 wherein said native instructions are of a Very Long Instruction Word (VLIW) format and wherein said non-native instructions are substantially compatible with the x86 instruction architecture.

12. The method of claim 9 wherein said event comprises a change in cacheability.

13. The method of claim 9 wherein said event is selected from the group consisting of interrupt handling and interrupt acceptance.