IP Library Granted Patent US 8,117,421
Granted Patent B2
US 8,117,421 · App. 12/688,722 · Granted Feb 14, 2012

Data structure for enforcing consistent per-physical page cacheability attributes

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,117,421
App. No.
12/688,722
Granted
Feb 14, 2012
Kind
B2
Abstract

A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

Claims (51)

1. A method comprising:

obtaining a first cacheability bit from a candidate entry that maps to a first physical page;

obtaining a second cacheability bit of said first physical page from a table that associates a physical page identifier with a current cacheability characteristic for physical pages;

comparing said first cacheability bit and said second cacheability bit;

responsive to a mismatch in said comparing, generating an exception and performing a fix-up operation, wherein said fix-up operation conforms said second cacheability bit with said first cacheability bit; and

entering said candidate entry into a translation lookaside buffer.

2. The method of claim 1 , wherein said first and said second cacheability bits comprise components of a data structure which is disposed in a memory and which provides information corresponding to the current cacheability characteristic of physical pages of said memory, wherein said data structure comprises a data field for identifying said current cacheability characteristic, wherein said data structure is indexed by said physical page identifier, and wherein said physical page identifier comprises a physical page number.

3. The method of claim 1 , wherein said first cacheability bit indicates cacheable and said second cacheability bit indicates non-cacheable and wherein said performing a fix-up operation comprises:

updating said current cacheability characteristic to non-cacheable; and

flushing a cache of said physical page.

4. The method of claim 1 , wherein said first cacheability bit indicates non-cacheable and said second cacheability bit indicates cacheable and wherein said performing a fix-up operation comprises:

draining a pending write from a non-cacheable path; and

updating said current cacheability characteristic to cacheable.

5. The method of claim 1 , wherein said performing a fix-up operation comprises:

determining that a mode of execution is aggressive;

rolling back to the last commit point in said execution;

changing said mode of execution to disallow speculation; and

repeating said execution without speculation until said exception is triggered again.

6. The method of claim 5 , wherein said first cacheability bit indicates cacheable and said second cacheability bit indicates non-cacheable and wherein said performing a fix-up operation comprises:

updating said current cacheability characteristic to non-cacheable; and

flushing a cache of said physical page.

7. The method of claim 5 , wherein said first cacheability bit indicates non-cacheable and said second cacheability bit indicates cacheable and wherein said performing a fix-up operation comprises:

draining a pending write from a non-cacheable path; and

updating said current cacheability characteristic to cacheable.

8. The method of claim 1 further comprising removing an old entry with said physical page identifier from said translation lookaside buffer.

9. A method comprising:

obtaining a first cacheability attribute from a candidate entry that maps to a first physical page;

obtaining a second cacheability attribute of said first physical page from a table that associates a physical page identifier with a current cacheability characteristic for physical pages;

comparing said first cacheability attribute and said second cacheability attribute;

responsive to a mismatch in said comparing, generating an exception and performing a fix-up operation, wherein said fix-up operation conforms said second cacheability attribute with said first cacheability attribute; and

entering said candidate entry into a translation lookaside buffer.

10. The method of claim 9 , wherein said first and said second cacheability attributes comprise components of a data structure which is disposed in a memory and which provides information corresponding to the current cacheability characteristic of physical pages of said memory, wherein said data structure comprises a data field for identifying said current cacheability characteristic, and wherein said data structure is indexed by said physical page identifier.

11. The method of claim 10 , wherein said physical page identifier comprises a physical page number.

12. The method of claim 10 , wherein said first cacheability attribute indicates cacheable and said second cacheability attribute indicates non-cacheable and wherein said performing a fix-up operation comprises:

updating said current cacheability characteristic to non-cacheable; and

flushing a cache of said physical page.

13. The method of claim 10 , wherein said first cacheability attribute indicates non-cacheable and said second cacheability attribute indicates cacheable and wherein said performing a fix-up operation comprises:

draining a pending write from a non-cacheable path; and

updating said current cacheability characteristic to cacheable.

14. The method of claim 10 , wherein said performing a fix-up operation comprises:

determining that a mode of execution is aggressive;

rolling back to the last commit point in said execution;

changing said mode of execution to disallow speculation; and

repeating said execution without speculation until said exception is triggered again.

15. The method of claim 14 , wherein said first cacheability attribute indicates cacheable and said second cacheability attribute indicates non-cacheable and wherein said performing a fix-up operation comprises:

updating said current cacheability characteristic to non-cacheable; and

flushing a cache of said physical page.

16. The method of claim 14 , wherein said first cacheability attribute indicates non-cacheable and said second cacheability attribute indicates cacheable and wherein said performing a fix-up operation comprises:

draining a pending write from a non-cacheable path; and

updating said current cacheability characteristic to cacheable.

17. The method of claim 9 further comprising removing an old entry with said physical page identifier from said translation lookaside buffer.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 6, 2015
From: INTELLECTUAL VENTURES FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036797/0356 →
MERGER Recorded Sep 29, 2015
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036711/0160 →