IP Library Granted Patent US 7,256,639
Granted Patent B1
US 7,256,639 · App. 10/956,218 · Granted Aug 14, 2007

Systems and methods for integrated circuits comprising multiple body bias domains

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Quick Facts
Patent No.
US 7,256,639
App. No.
10/956,218
Granted
Aug 14, 2007
Kind
B1
Abstract

Systems and methods for integrated circuits comprising multiple body bias domains. In accordance with a first embodiment of the present invention, an integrated circuit is constructed comprising active semiconductor devices in first and second body bias domains. A first body biasing voltage is coupled to the first body bias domain, and a second body biasing voltage is coupled to the second body bias domain. The first and the second body biasing voltages are adjusted to achieve a desirable relative performance between the active semiconductor devices in the first and the second body bias domains.

Claims (37)

1. A method of operating an integrated circuit comprising:

applying a body biasing voltage to an output cell of said integrated circuit;

accessing at said output cell a first signal to be output from said integrated circuit;

wherein said first signal is generated from circuitry of said integrated circuit that is separate from said body biasing voltage; and

outputting a second signal from said output cell corresponding to said first signal.

2. A method according to claim 1 wherein said second signal comprises a desirable slew rate.

3. A method according to claim 1 wherein said second signal comprises a slew rate that is less than a slew rate characteristic of said output cell without application of said body biasing voltage.

4. A method according to claim 1 wherein said integrated circuit comprises a microprocessor.

5. A method according to claim 1 wherein said circuitry and said output cell operate at different operating voltages.

6. A method according to claim 1 further comprising:

changing said body biasing voltage to a second body biasing voltage.

7. A method according to claim 6 wherein said body biasing voltage and said second body biasing voltage correspond to first and second operating frequencies of said integrated circuit.

8. An integrated circuit comprising an output cell disposed for receiving a body biasing voltage, wherein said body biasing voltage is operable to modify a slew rate of a signal output from said output cell.

9. An integrated circuit according to claim 8 wherein said body biasing voltage is separate from other circuitry of said integrated circuitry.

10. An integrated circuit according to claim 8 wherein an applied body bias voltage is operable to decrease a slew rate of a signal output from said output cell relative to a slew rate of a signal output from said output cell without application of said body bias voltage.

11. An integrated circuit according to claim 8 wherein said output cell is disposed to accept a plurality of body biasing voltage values to produce a plurality of slew rate outputs from said output cell.

12. A method of operating an integrated circuit comprising:

applying a first body biasing voltage to first circuitry of a first body bias domain;

applying a second body biasing voltage to second circuitry of a second body bias domain, wherein said first and said second body bias domains are electrically independent of one another; and

accessing a signal between said first and said second circuitry.

13. A method according to claim 12 wherein said applying said first body biasing voltage causes said first circuitry to switch faster than said first circuitry would switch without application of said first body biasing voltage.

14. A method according to claim 13 wherein said first circuitry does not produce a desired function without application of said first body biasing voltage.

15. A method according to claim 12 wherein said applying said first body biasing voltage causes said first circuitry to comprise less leakage current than said first circuitry would comprise without application of said first body biasing voltage.

16. A method according to claim 12 wherein application of said first body biasing voltage causes said first circuitry to switch faster than said first circuitry would switch without application of said first body biasing voltage and application of said second body biasing voltage causes said second circuitry to switch slower than said second circuitry would switch without application of said second body biasing voltage.

17. A method according to claim 12 wherein said signal is generated by said first circuitry and accessed by said second circuitry.

18. An integrated circuit comprising:

a first body bias domain comprising first circuitry;

a second body bias domain comprising second circuitry;

wherein said first and said second body bias domains are electrically independent of one another;

wherein said first and second body circuitries are disposed to receive first and second body biasing voltages;

a signal coupling between said first and second circuitry; and

wherein said first and second body biasing voltages are operable to modify operational characteristics of said first and second circuitry.

19. An integrated circuit according to claim 18 wherein said first circuitry is characterized having less leakage current with said first body biasing voltage applied than without said first body biasing voltage.

20. An integrated circuit according to claim 18 wherein said first circuitry switches faster with said first body biasing voltage applied than without application of said first body biasing voltage.

21. An integrated circuit according to claim 18 wherein said second circuitry switches slower with said first body biasing voltage applied than without application of said second body biasing voltage.

22. An integrated circuit according to claim 18 wherein said first circuitry requires application of said first body biasing voltage to perform a desired function.

23. An integrated circuit according to claim 18 wherein said signal is generated by said first circuitry and accessed by said second circuitry.

Assignments (8)
CHANGE OF NAME Recorded Jan 27, 2022
From: FACEBOOK, INC.
To: META PLATFORMS, INC.
Reel/Frame 058871/0336 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2019
From: INTELLECTUAL VENTURES ASSETS 88 LLC
To: FACEBOOK, INC.
Reel/Frame 048136/0179 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2018
From: INTELLECTUAL VENTURES HOLDING 81 LLC
To: INTELLECTUAL VENTURES ASSETS 88 LLC
Reel/Frame 047014/0629 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 6, 2015
From: INTELLECTUAL VENTURES FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036797/0356 →
MERGER Recorded Sep 29, 2015
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036711/0160 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2009
From: TRANSMETA LLC
To: INTELLECTUAL VENTURE FUNDING LLC
Reel/Frame 023268/0771 →
MERGER Recorded Mar 26, 2009
From: TRANSMETA CORPORATION
To: TRANSMETA LLC
Reel/Frame 022454/0522 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2004
From: KONIARIS, KLEANTHES G.; BURR, JAMES B.
To: TRANSMETA CORPORATION
Reel/Frame 015885/0543 →