Clock signal distribution system and method

1. An integrated circuit clock distribution system comprising:

a plurality of clocked components;

a clock grid mesh for distributing a clock signal to said clocked components; and

a diagonal offset clock signal distribution tree for distributing a clock signal to said clock grid mesh, wherein said diagonal offset clock signal distribution tree and a power distribution grid are included in a top metal layer of an integrated circuit and opposing intermediate downstream branches of said diagonal offset clock signal distribution tree are offset on an intermediate upstream branch; and

pads for communicatively coupling external components to said power distribution grid, wherein said offset is wider than said pads.

2. An integrated circuit clock distribution system of claim 1 wherein said diagonal offset clock signal distribution tree forms a uniform array of end points that said clocked components are tapped into.

3. An integrated circuit clock distribution system of claim 1 wherein endpoints of said diagonal offset clock signal distribution tree are symmetrical from a central clock point.

4. An integrated circuit clock distribution system of claim 1 further comprising a ground grid for providing a ground to said plurality of clocked components.

5. An integrated circuit clock distribution formation method:

forming a layer of clocked functional components in an integrated circuit;

depositing a clock grid mesh for distributing a clock signal to said clocked functional components; and

developing a diagonal offset clock signal distribution tree for distributing said clock signal to said clock grid mesh, wherein said diagonal offset clock signal distribution tree is in a single layer and opposing intermediate downstream branches of said diagonal offset clock signal distribution tree are offset on an intermediate upstream branch and said offset is wider than a pad.

6. An integrated circuit clock distribution formation method of claim 5 wherein photolithography is utilized to form said diagonal offset clock signal distribution tree.

7. An integrated circuit clock distribution formation method of claim 6 wherein a photolithographic mask template is an offset Y configuration.

8. An integrated circuit clock distribution formation method of claim 6 wherein endpoints of said diagonal offset clock signal distribution tree are equidistant from a central clock source.

9. An integrated circuit clock distribution formation method of claim 6 wherein supplemental routes are added to said clock grid mesh.

10. An integrated circuit clock distribution formation method of claim 6 wherein vertical vias couple endpoints of said diagonal offset clock signal distribution tree in a first layer to said clock grid mesh in a second layer.

11. An integrated circuit clock distribution formation method of claim 6 wherein offset paths in said diagonal offset clock signal distribution tree couple vertical runs in said clock grid mesh.

12. An integrated circuit clock distribution formation method of claim 6 wherein paths of said diagonal offset clock signal distribution tree do not come back on one another between two adjacent pads.

13. An integrated circuit clock distribution formation method of claim 6 wherein said diagonal offset clock signal distribution tree distributes signals in a single clock domain.

14. An integrated circuit clock distribution system comprising:

a means for performing functional operations; and

a means for distributing a clock signal, wherein said means includes diagonally offset branches and opposing intermediate downstream branches are offset on an intermediate upstream branch and said offset is wider than a pad, wherein said means for distributing a clock signal includes a diagonal offset clock signal distribution tree in a single layer.

15. An integrated circuit clock distribution system of claim 14 wherein endpoints of said means for distributing said clock signal are symmetrically equidistant from a central clock distribution point.