IP Library Granted Patent US 7,242,205
Granted Patent B1
US 7,242,205 · App. 11/136,038 · Granted Jul 10, 2007

System and method for reducing heat dissipation during burn-in

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Quick Facts
Patent No.
US 7,242,205
App. No.
11/136,038
Granted
Jul 10, 2007
Kind
B1
Abstract

Systems and methods for reducing temperature dissipation during burn-in testing are described. A plurality of devices under test are each subject to a body bias voltage. The body bias voltage reduces leakage current associated with the devices under test. Accordingly, heat dissipation is reduced during burn-in. The body bias voltage is selected to achieve a desired junction temperature at the devices under test.

Claims (29)

1. An apparatus for burn-in testing comprising:

a plurality of devices under test, each of said devices under test subject to a body bias voltage;

a test controller coupled to said devices under test, wherein said test controller accesses a store of information comprising leakage current as a function of body bias voltage and selects a body bias voltage that corresponds to the minimum leakage current in said store of information;

a voltage supply for providing said body bias voltage corresponding to said minimum leakage current to said devices under test, wherein said body bias voltage corresponding to said minimum leakage current reduces junction temperature at said devices under test; and

a wiring board for coupling said devices under test and said voltage supply.

2. The apparatus of claim 1 further comprising a second voltage supply for providing an operating voltage to said devices under test.

3. The apparatus of claim 1 wherein said devices under test comprise positive-channel metal-oxide semiconductor (PMOS) devices.

4. The apparatus of claim 3 wherein said body bias voltage is in the range of approximately zero to five volts.

5. The apparatus of claim 1 wherein said devices under test comprise negative-channel metal-oxide semiconductor (NMOS) devices.

6. The apparatus of claim 5 wherein said body bias voltage is in the range of approximately zero to minus ten volts.

7. A method of burn-in testing of a plurality of devices under test, said method comprising:

applying an operating voltage to said devices under test;

accessing a store of information comprising leakage current indexed by body bias voltage;

selecting from said store of information a body bias voltage that minimizes leakage current for said devices under test; and

applying said body bias voltage to said devices under test, wherein application of said body bias voltage reduces leakage current associated with said devices under test and wherein said body bias voltage is selected to achieve a desired junction temperature at said devices under test.

8. The method of claim 7 wherein said devices under test comprise positive-channel metal-oxide semiconductor (PMOS) devices.

9. The method of claim 8 wherein said body bias voltage is in the range of approximately zero to five volts.

10. The method of claim 7 wherein said devices under test comprise negative-channel metal-oxide semiconductor (NMOS) devices.

11. The method of claim 10 wherein said body bias voltage is in the range of approximately zero to minus ten volts.

12. A method of burn-in testing of a plurality of devices, said method comprising:

prior to said burn-in testing, testing said devices to measure leakage current as a function of body bias voltage;

storing information comprising leakage current indexed by body bias voltage, said information specific to said devices;

accessing said information;

selecting a body bias voltage that substantially minimizes leakage current associated with said devices; and

during said burn-in testing, applying said body bias voltage to said devices in addition to an operating voltage applied to said devices, wherein said operating voltage in combination with said body bias voltage achieves a desired junction temperature at said devices.

13. The method of claim 12 wherein said devices comprise positive-channel metal-oxide semiconductor (PMOS) devices.

14. The method of claim 13 wherein said body bias voltage is in the range of approximately zero to five volts.

15. The method of claim 12 wherein said devices comprise negative-channel metal-oxide semiconductor (NMOS) devices.

16. The method of claim 15 wherein said body bias voltage is in the range of approximately zero to minus ten volts.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 6, 2015
From: INTELLECTUAL VENTURES FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036797/0356 →
MERGER Recorded Sep 29, 2015
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036711/0160 →