Interpage prologue to protect virtual address mappings
View Patent ↗In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.
1. A method of determining validity of a translated instruction comprising:
a) starting execution of a succeeding host instruction translated from a first target instruction, wherein said succeeding host instruction is linked via a jump command from a preceding host instruction translated from a second target instruction, and wherein a first condition of a target system state required by said first succeeding host instruction holds, wherein said first condition is based on an address consistency check of said preceding host instruction;
b) testing a second condition of said target system state to determine the validity of said succeeding host instruction;
c) executing said succeeding host instruction if said second condition holds; and
d) generating an exception if said second condition does not hold.
2. The method of claim 1 , wherein said b) comprises performing an address consistency check of said succeeding host instruction.
3. The method of claim 2 , wherein said b) comprises comparing a physical address of said first target instruction against an address stored in said succeeding host instruction.
4. The method of claim 1 , wherein said first condition is that an address stored in said preceding host instruction matches a physical address of said second target instruction.
5. The method of claim 4 , wherein said b) comprises verifying that an address stored in said succeeding host instruction matches a physical address of said first target instruction.
6. The method of claim 1 , wherein said d) further comprises invalidating said succeeding host instruction.
7. The method of claim 1 , wherein said d) further comprises removing said jump command between said succeeding host instruction and said preceding host instruction.
8. The method of claim 1 , wherein said d) further comprises creating a new translation of said first target instruction.
9. The method of claim 1 , wherein said d) further comprises interpreting said first target instruction.
10. A method of determining validity of a translated instruction comprising:
a) performing a first address consistency check of a first host instruction made from a first target instruction to verify that said first host instruction is valid;
b) executing said first host instruction;
c) determining whether a second host instruction made from a second target instruction and that is linked via jump command from said first host instruction can be safely executed without a second address consistency check by determining whether said first and second target instructions are on a same memory page; and
d) executing said second host instruction without performing said second address consistency check if safe.
11. The method of claim 10 , further comprising:
e) performing said second address consistency check if said determination is that it is unsafe to execute said second host instruction without said second address consistency check; and
f) executing said second host instruction if said second address consistency check passes.
12. A method of linking translated instructions comprising:
a) translating a first target instruction to a first host instruction;
b) translating a second target instruction to a second host instruction;
c) determining at the time said translation of said second target instruction is made that said first and second host instructions are to be linked; and
d) providing an address consistency check for said second host instruction by:
linking said first host instruction to said second host instruction via a jump command; and
including code for performing said address consistency check as a part of said second host instruction.
13. A method of translated instructions comprising:
a) translating a first target instruction to a first host instruction;
b) translating a second target instruction to a second host instruction;
c) determining after said translation of said second target instruction is made that said first and second host instructions are to be linked; and
d) providing an address consistency check for said second host instruction by:
linking said first host instruction to code for performing said address consistency check via a first jump command; and
linking said code for performing said address consistency check to said second host instruction via a second jump command.
14. A method of linking translated instructions comprising:
a) translating a first target instruction to a first host instruction;
b) translating a second target instruction to a second host instruction;
c) determining after said translation of said second target instruction is made that said first and second host instructions are to be linked; and
c) comprises:
d) providing an address consistency check for said second host instruction by:
linking said first host instruction to said second host instruction via a jump command; and
incorporating code for performing said address consistency check into said second host instruction.