IP Library › Assignment 011566/0681

Patent Assignment

Reel/Frame 011566/0681

Merger

Recorded: 2001-02-13 Pages: 11

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Assignor

TRANSMETA CORPORATION, A CALIFORNIA CORPORATION

Executed: 2000-10-26

Assignee

TRANSMETA CORPORATION

A DELAWARE CORPORATION, 3940 FREEDOM CIRCLE, SANTA CLARA, CALIFORNIA, 95054

Covered Properties (43)

Combining Hardware and Software to Provide an Improved Microprocessor

Patent: 6,031,992 →

Application: 08/678,541 →

Host Microprocessor with Apparatus for Temporarily Holding Target Processor State

Patent: 5,958,061 →

Application: 08/685,721 →

A Memory Controller for a Microprocessor for Detecting a Failure of Speculation on the Physical Nature of a Component Being Addressed

Patent: 5,832,205 →

Application: 08/700,302 →

Translated Memory Protection Apparatus for an Advanced Microprocessor

Patent: 6,199,152 →

Application: 08/702,771 →

Nethod and Apparatus for Aliasing Memory Data in an Advanced Microprocessor

Patent: 5,926,832 →

Application: 08/721,698 →

A Gated Store Buffer for an Advanced Microprocessor

Patent: 6,011,908 →

Application: 08/772,686 →

Method and Apparatus for Correcting Errors in Computer Systems

Patent: 5,905,855 →

Application: 08/807,542 →

Noncontact Temperature Distribution Measuring Apparatus

Patent: 6,089,750 →

Application: 09/159,628 →

Method and Apparatus for Enhancing Scheduling in an Advanced Microprocessor

Patent: 7,089,404 →

Application: 09/332,338 →

Memory Array Bitline Timing Circuit

Patent: 6,172,925 →

Application: 09/333,178 →

Method for Switching Between Interpretation and Dynamic Translation in a Processor System Based Upon Code Sequence Execution Counts

Patent: 7,761,857 →

Application: 09/417,332 →

Fine Grain Translation Discrimination

Patent: 6,363,336 →

Application: 09/417,356 →

System for Using Rate of Exception Event Generation During Execution of Translated Instructions to Control Optimization of the Translated Instructions

Patent: 6,714,904 →

Application: 09/417,358 →

Programmable Event Counter System

Patent: 6,356,615 →

Application: 09/417,930 →

Method of Optimizing Compiler Vs Interpreter Mode Operation in a Code Translator Based Upon Amount of Time Spent in Each Mode

Patent: 6,880,152 →

Application: 09/417,979 →

Method for Translating Instructions in a Speculative Microprocessor Featuring Committing State

Patent: 6,990,658 →

Application: 09/417,980 →

Method and Apparatus for Maintaining Context While Executing Translated Instructions

Patent: 6,415,379 →

Application: 09/417,981 →

Pipeline Replay Support for Unaligned Memory Operations

Patent: 6,728,865 →

Application: 09/420,748 →

Method for Increasing the Speed of Speculative Execution

Patent: 6,748,589 →

Application: 09/421,484 →

Electrostatic Discharge Protection for Mosfets

Patent: 6,429,491 →

Application: 09/421,614 →

Publication: US 2002/0070408

Use of Enable Bits to Control Execution of Selected Instructions

Patent: 6,738,892 →

Application: 09/421,615 →

Pipeline Replay Support for Multi-Cycle Operations Wherein All Vliw Instructions Are Flushed Upon Detection of a Multi-Cycle Atom Operation in a Vliw Instruction

Patent: 6,604,188 →

Application: 09/421,972 →

Instruction Packing for an Advanced Microprocessor

Patent: 6,754,892 →

Application: 09/464,638 →

Check Instruction and Method

Patent: 6,513,110 →

Application: 09/464,644 →

Interpage Prologue to Protect Virtual Address Mappings

Patent: 6,845,353 →

Application: 09/471,447 →

Adaptive Power Control

Patent: 7,100,061 →

Application: 09/484,516 →

Publication: US 2002/0116650

Translation Consistency Checking for Modified Target Instructions by Comparing to Original Copy

Patent: 6,594,821 →

Application: 09/539,987 →

Method and Apparatus for Scheduling to Reduce Space and Increase Speed of Microprocessor Operations

Patent: 6,738,893 →

Application: 09/557,650 →

Cache Memory Array for Multiple Address Spaces

Patent: 6,571,316 →

Application: 09/595,077 →

Apparatus for controlling semiconductor chip characteristics

Application: 09/595,196 →

System and Method for Preserving Internal Processor Context When the Processor Is Powered Down and Restoring the Internal Processor Context When Processor Is Restored

Patent: 6,968,469 →

Application: 09/595,198 →

Method and Apparatus for Emulating a Floating Point Stack in a Translation Process

Patent: 6,725,361 →

Application: 09/595,199 →

Fast Look-Up of Indirect Branch Destination in a Dynamic Translation System

Patent: 6,615,300 →

Application: 09/596,279 →

Floating Point Exception Handling in Pipelined Processor Using Special Instruction to Detect Generated Exception and Execute Instructions Singly from Known Correct State

Patent: 6,826,682 →

Application: 09/603,743 →

Saving Power When in or Transitioning to a Static Mode of a Processor

Patent: 7,260,731 →

Application: 09/694,433 →

Translated Memory Protection Apparatus for an Advanced Microprocessor

Patent: 7,840,776 →

Application: 09/699,947 →

Inner Laminated Woven Bag for Food Packaging

Patent: 9,714,118 →

Application: 13/585,569 →

Publication: US 2013/0040084