Method and apparatus for enhancing scheduling in an advanced microprocessor
View Patent ↗Apparatus and a method for causing scheduler software to produce code which executes more rapidly by ignoring some of the normal constraints placed on its scheduling operations and simply scheduling certain instructions to run as fast as possible, raising an exception if the scheduling violates a scheduling constraint, and determining steps to be taken for correctly executing each set of instructions about which an exception is raised.
1. An apparatus comprising:
a processor operable to execute a reordered sequence of instructions, wherein the reordered sequence of instructions includes a first instruction and a second instruction to be changed from being executable after the first instruction to being executable prior to the first instruction;
a register operable to store, if the second instruction is executed, a first memory address range accessed by the second instruction, wherein the register is unusable by the reordered sequence of instructions, and wherein the first instruction includes information that indicates in a bitmask of the first instruction, which is affected by the reordering, to identify the register; and
a comparator coupled to the register, wherein the comparator is operable to compare the first memory address range with a second memory address range accessed by the first instruction to determine an overlap responsive to an enable signal, wherein if the comparator determines the first memory address range overlaps the second memory address range, an exception is triggered.
2. The apparatus of claim 1 , wherein at least one of the first instruction and the second instruction is a store instruction.
3. The apparatus of claim 1 , wherein at least one of the first instruction and the second instruction is a load instruction.
4. The apparatus of claim 1 , further comprising an exception handler.
5. The apparatus of claim 1 , wherein the reordered sequence of instructions comprises a plurality of instructions translated from a plurality of source instructions.
6. The apparatus of claim 1 , wherein the information enables a comparison result from the comparator.
7. An apparatus comprising:
a processor operable to execute a modified sequence of instructions, wherein the modified sequence of instructions includes a first instruction, wherein the modified sequence of instructions are operable to omit a second instruction of an unmodified sequence of instructions including the first instruction and the second instruction;
a register operable to store a first memory address range associated with the second instruction, wherein the register is unusable by the modified sequence of instructions, and wherein the first instruction includes information that indicates in a bitmask of the first instruction, which is affected by the omission of the second instruction, to identify the register; and
a comparator coupled to the register, wherein the comparator is operable to compare the first memory address range with a second memory address range accessed by the first instruction to determine an overlap responsive to an enable signal, wherein if the comparator determines the first memory address range overlaps the second memory address range, an exception is triggered.
8. The apparatus of claim 7 , wherein at least one of the first instruction and the second instruction is a store instruction.
9. The apparatus of claim 7 , wherein at least one of the first instruction and the second instruction is a load instruction.
10. The apparatus of claim 7 , further comprising an exception handler.
11. The apparatus of claim 7 , wherein the modified sequence of instructions comprises a plurality of instructions translated from a plurality of source instructions.
12. The apparatus of claim 7 , wherein the information enables a comparison result from the comparator.
13. An apparatus comprising:
means for executing a reordered sequence of instructions, wherein the reordered sequence of instructions includes a first instruction and a second instruction to be changed from being executable after the first instruction to being executable prior to the first instruction;
means for storing, if the second instruction is executed, a first memory address range accessed by the second instruction, wherein the means for storing is unused by the reordered sequence of instructions, and wherein the first instruction includes information that indicates in a bitmask of the first instruction, which is affected by the reordering, to identify the means for storing; and
means for comparing the first memory address range with a second memory address range accessed by the first instruction to determine an overlap responsive to an enable signal, wherein the means for comparing is coupled to the means for storing, wherein if the means for comparing determines the first memory address range overlaps the second memory address range, an exception is triggered.
14. The apparatus of claim 13 , wherein at least one of the first instruction and the second instruction is a store instruction.
15. The apparatus of claim 13 , wherein at least one of the first instruction and the second instruction is a load instruction.
16. The apparatus of claim 13 , wherein the reordered sequence of instructions comprises a plurality of instructions translated from a plurality of source instructions.
17. The apparatus of claim 13 , wherein the information enables a result from the means for comparing.