Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine
View Patent ↗A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine. The method includes executing a host machine application within a host machine context and executing a virtual machine application within a virtual machine context. A plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context are stored within a TLB. Memory protection bits for the plurality of TLB entries are logically combined to enforce memory protection on the virtual machine application.
1. A method for providing hardware support for memory protection and virtual memory address translation for a virtual machine, comprising:
executing a host machine application within a host machine context;
executing a virtual machine application within a virtual machine context;
storing a plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context within a TLB; and
using a logical AND to combine a plurality of memory protection bits, wherein at least one of the memory protection bits is a dirty bit, for the plurality of TLB entries to enforce memory protection the virtual machine application.
2. The method of claim 1 wherein at least one of the memory protection bits is a read/write bit.
3. The method of claim 1 wherein the host machine application is a host machine operating system that executes within the host machine context and the virtual machine application is a virtual machine operating system that executes within the virtual machine context.
4. The method of claim 1 wherein the TLB entries include respective context identifiers enabling the TLB entries to provide physical address translation for virtual addresses from both the host machine context and the virtual machine context.
5. The method of claim 1 further comprising:
updating the TLB with new entries when a virtual machine TLB miss occurs or a host machine TLB miss occurs.
6. A system for providing hardware support for memory protection and virtual memory address translation for a virtual machine, comprising:
a processor architecture including micro architecture code configured to execute natively on a CPU hardware unit of the processor architecture; and
an address translation cache for implementing a translation look aside buffer, with the address translation cache in conjunction with the processor architecture implementing a method comprising:
executing a host machine application within a host machine context;
executing a virtual machine application within a virtual machine context;
storing a plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context within a TLB; and
using a logical AND to combine a plurality of memory protection bits, wherein at least one of the memory protection bits is a dirty bit, for the plurality of TLB entries to enforce memory protection on the virtual machine application.
7. The system of claim 6 wherein at least one of the memory protection bits is a read/write bit.
8. The system of claim 6 wherein the host machine application is a host machine operating system that executes within the host machine context and the virtual machine application is a virtual machine operating system that executes within the virtual machine context.
9. The system of claim 6 wherein the TLB entries include respective context identifiers enabling the TLB entries to provide physical address translation for virtual addresses from both the host machine context and the virtual machine context.
10. The system of claim 6 further comprising:
updating the TLB with new entries when a virtual machine TLB miss occurs or a host machine TLB miss occurs.
11. A computer readable media for providing hardware support for memory protection and virtual memory address translation for a virtual machine, the media storing computer readable code which when executed by a processor causes the processor to implement a method comprising:
executing a host machine application within a host machine context;
executing a virtual machine application within a virtual machine context;
storing a plurality of TLB (translation look aside buffer) entries for the virtual machine context and the host machine context within a TLB; and
using a logical AND to combine a plurality of memory protection bits, wherein at least one of the memory protection bits is a read/write bit, for the plurality of TLB entries to enforce memory protection on the virtual machine application.
12. The computer readable media of claim 11 wherein at least one of the memory protection bits is a dirty bit.
13. The computer readable media of claim 11 wherein the host machine application is a host machine operating system that executes within the host machine context and the virtual machine application is a virtual machine operating system that executes within the virtual machine context.
14. The computer readable media of claim 11 wherein the TLB entries include respective context identifiers enabling the TLB entries to provide physical address translation for virtual addresses from both the host machine context and the virtual machine context.
15. The computer readable media of claim 11 further comprising:
updating the TLB with new entries when a virtual machine TLB miss occurs or a host machine TLB miss occurs.