Systems and methods for voltage distribution via epitaxial layers

1. An integrated circuit comprising:

a wafer substrate of a first conduction type;

an epitaxial layer of a second conduction type;

a plurality of wells of the first conduction type disposed within said epitaxial layer;

a plurality of deep wells of said first conduction type, wherein at least one of said plurality of deep wells couples at least one of said plurality of wells to said wafer substrate and another of said plurality of deep wells couples another of said plurality of wells to said wafer substrate;

a first tap of said second conduction type disposed within at least a first portion of said epitaxial layer for coupling a first body biasing voltage to at least a first portion of said epitaxial layer; and

a second tap of said first conduction type disposed within said one of said plurality of wells for coupling a second body biasing voltage to said another of said plurality of wells through said one and said another of said plurality of deep wells and said substrate layer.

2. The integrated circuit of claim 1 wherein said second body biasing voltage is conducted substantially vertically within saidl plurality of deep wells.

3. The integrated circuit of claim 1 further comprising:

a first plurality of field effect transistors formed in said epitaxial layer;

a second plurality of field effect transistors formed in said another of said plurality of wells.

4. The integrated circuit of claim 1 wherein said first body biasing voltage is conducted substantially laterally within said epitaxial layer.

5. The integrated circuit of claim 1 further comprising a region of said epitaxial layer electrically isolated from other portions of said epitaxial layer.

6. The integrated circuit of claim 5 further comprising:

said one of said plurality of deep wells couples said one of said plurality of wells to said substrate to form an isolation structure of an isolation tub portion of said epitaxial layer;

a third plurality of field effect transistors formed in said isolation tub; and

a fourth plurality of field effect transistors formed in at least one of said plurality of wells in said isolation tub.

7. The integrated circuit of claim 6 further comprising:

a third tap of said second connection type coupling a third body biasing voltage to said isolation tub portion of said epitaxial layer; and

a fourth tap of said first connectivity type coupling a fourth body biasing voltage to said at least one well in said isolation tub.

8. The integrated circuit of claim 7 , wherein said first and second body biasing voltages forms a first body biasing domain and said third and fourth body biasing voltages form a second body biasing domain different from said first body biasing domain.

9. An integrated circuit comprising:

a first plurality of field effect transistors formed in an epitaxial layer of a first conduction type;

a second plurality of field effect transistors formed in a first well of second conduction type opposite said first conduction type, said well disposed within said epitaxial layer;

a layer of said second conduction type disposed beneath said epitaxial layer; and

a deep well of said second conduction type for coupling a first body biasing voltage from a second well of said second conductivity type disposed within said epitaxial layer through said layer to said second plurality of field effect transistors wherein said deep well does not form an isolating structure.

10. The integrated circuit of claim 9 further comprising a tap of said first conduction type formed in said epitaxial layer for coupling a second body biasing voltage to said first plurality of field effect transistors.

11. The integrated circuit of claim 10 wherein conduction of said second body biasing voltage is substantially lateral within said epitaxial layer.