Pipeline replay support for unaligned memory operations
View Patent ↗Instructions asserted in a microprocessors instruction pipeline ( 3 ) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline ( 5 ) that is synchronized to the instruction pipeline. At the execution stage, the control information is interpreted and appropriate action taken. The control information may indicate that the instruction has been reasserted (asserted again following an initial assertion) and may also indicate the number of times that the instruction has been consecutively asserted in the instruction pipeline. Applied to unaligned memory operations, in which a memory atom is asserted twice, the control information indicates which part of the unaligned data is to be fetched each time the atom is executed.
1. A method of computer processing for handling unaligned memory operations comprising:
fetching a first unaligned data segment from memory;
storing said first unaligned data segment in a register;
fetching a second unaligned data segment from memory;
retrieving said first unaligned data segment from said register; and
merging said first unaligned data segment and said second unaligned data segment in accordance with control data corresponding to said first unaligned data segment and said second unaligned data segment, wherein said instruction is one of a plurality of atom instructions comprising a molecule instruction, and wherein any atom instructions of said molecule instruction not relating to said unaligned memory operation are disabled until said merging is performed.
2. The method of claim 1 , wherein said fetching is performed in response to an instruction asserted in an instruction pipeline.
3. The method of claim 2 , wherein said instruction pipeline is flushed before said instruction is asserted.
4. The method of claim 3 , wherein the operation of said instruction pipeline is halted before said flushing is performed.
5. The method of claim 1 , wherein said disabling is performed by changing the state of enable bits.
6. The method of claim 1 , wherein said control data is asserted into a control information pipeline.
7. The method of claim 1 , wherein said control data comprises a plurality of help bits.
8. A computer processor for handling unaligned memory operations comprising:
a register for storing unaligned data segments fetched from memory;
an instruction pipeline for conveying asserted instructions;
a control information pipeline for conveying control data;
a pipeline control unit for asserting said instructions to said instruction pipeline, and for asserting said control data to said control information pipeline; and
a functional execution unit for fetching a first unaligned data segments from memory in response to one or more of said asserted instructions, for causing said first unaligned data segments to be stored in said register, for fetching a second unaligned data segments from memory in response to one or more of said asserted instructions, for retrieving said first unaligned data segments from said register, and for merging said first unaligned data segments and said second unaligned data segments in accordance with control data corresponding to said first unaligned data segments and said second unaligned data segments, wherein said instruction pipeline is flushed before conveying said asserted instructions.
9. The processor of claim 8 , wherein the operation of said instruction pipeline is halted before said flushing is performed.
10. The processor of claim 8 , wherein said asserted instructions are one or more of a plurality of atom instructions comprising a molecule instruction.
11. The processor of claim 10 , wherein any atom instructions of said molecule instruction not relating to said unaligned memory operation are disabled until said merging is performed, and wherein said disabling is performed by changing the state of one or more enable bits.
12. The processor of claim 8 , wherein said control data is asserted into a control information pipeline.
13. The processor of claim 8 , wherein said control data comprises a plurality of help bits.
14. A computer system for handling unaligned memory operations comprising:
a memory for storing computer-readable code; and
a central processing unit coupled to said memory comprising:
a register for storing unaligned data segments fetched from said memory;
an instruction pipeline for conveying asserted instructions;
a control information pipeline for conveying control data;
a pipeline control unit for asserting said instructions to said instruction pipeline, and for asserting said control data to said control information pipeline; and
a functional execution unit for fetching a first unaligned data segments from said memory in response to one or more of said asserted instructions, for causing said first unaligned data segments to be stored in said register, for fetching a second unaligned data segments from said memory in response to one or more of said asserted instructions, for retrieving said first unaligned data segments from said register, and for merging said first unaligned data segments and said second unaligned data segments in accordance with control data corresponding to said first unaligned data segments and said second unaligned data segments, wherein said asserted instructions are one or more of a plurality of atom instructions comprising a molecule instruction, wherein any atom instructions of said molecule instruction not relating to said unaligned memory operation are disabled until said merging is performed, and wherein said disabling is performed by changing the state of one or more enable bits.
15. The computer system of claim 14 , wherein said control data comprises a plurality of help bits.