Data structure for enforcing consistent per-physical page cacheability attributes
View Patent ↗A data structure for enforcing consistent per-physical page cacheability attributes is disclosed. The data structure is used with a method for enforcing consistent per-physical page cacheability attributes, which maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.
1. A non-transitory computer-readable storage device comprising a data structure stored therein, the data structure comprising:
a first field operable to store a current cacheability attribute for a memory page in memory and to store an updated current cacheability attribute for the memory page responsive to a mismatch between the current cacheability attribute and a cacheability attribute of a candidate entry for a translation lookaside buffer (TLB), wherein a physical address of the candidate entry is within a range of physical addresses associated with the memory page; and
a second field operable to store a memory page identifier for the memory page,
wherein the memory page in the memory is accessible via a cacheable data path that is separate from the data structure and is accessible via a non-cacheable data path that is separate from the data structure.
2. The non-transitory computer-readable storage device of claim 1 , wherein the memory page identifier comprises a page number corresponding to the memory page.
3. The non-transitory computer-readable storage device of claim 1 , further comprising a private memory, wherein the data structure is stored in the private memory.
4. The non-transitory computer-readable storage device of claim 1 , wherein the current cacheability attribute indicates cacheable.
5. The non-transitory computer-readable storage device of claim 1 , wherein the current cacheability attribute indicates non-cacheable.
6. The non-transitory computer-readable storage device of claim 1 , wherein the current cacheability attribute is determined by data path used in most recent access to the memory page.
7. An apparatus comprising:
a first memory including a plurality of memory pages; and
a second memory including a data structure, wherein the data structure comprises:
a first field operable to store a current cacheability attribute for a memory page of the first memory and to store an updated current cacheability attribute for the memory page responsive to a mismatch between the current cacheability attribute and a cacheability attribute of a candidate entry for a translation lookaside buffer (TLB), wherein a physical address of the candidate entry is within a range of physical addresses associated with the memory page; and
a second field operable to store a memory page identifier for the memory page,
wherein the memory page in the first memory is accessible via a cacheable data path that is separate from the data structure and is accessible via a non-cacheable data path that is separate from the data structure.
8. The apparatus of claim 7 , wherein the memory page identifier comprises a page number corresponding to the memory page.
9. The apparatus of claim 7 , wherein the second memory is a private memory.
10. The apparatus of claim 7 , wherein the current cacheability attribute indicates cacheable.
11. The apparatus of claim 7 , wherein the current cacheability attribute indicates non-cacheable.
12. The apparatus of claim 7 , wherein the current cacheability attribute is determined by data path used in most recent access to the memory page.
13. A method comprising:
comparing a cacheability attribute of a candidate entry for a translation lookaside buffer (TLB) with a current cacheability attribute for a physical address of the candidate entry, wherein a data structure is operable to store the current cacheability attribute, wherein the data structure comprises a first field operable to store the current cacheability attribute for a memory page and a second field operable to store a memory page identifier for the memory page, and wherein the memory page is accessible via a cacheable data path and is accessible via a non-cacheable data path; and
responsive to a mismatch in the comparing, updating the data structure with an updated current cacheability attribute.
14. The method of claim 13 , wherein the memory page identifier comprises a page number corresponding to the memory page.
15. The method of claim 13 , further comprising:
responsive to a match in the comparing, storing the candidate entry in the TLB.
16. The method of claim 13 , wherein the updating comprises:
determining an execution mode.
17. The method of claim 16 , wherein the execution mode is one of an aggressive execution mode and a conservative execution mode.