Method and system for caching attribute data for matching attributes with physical addresses
View Patent ↗A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.
1. A method comprising:
accessing a logic to compute at least one attribute for a physical address in response to a translation look aside buffer (TLB) miss and an attribute cache miss; and
storing the at least one attribute and the physical address in an attribute cache.
2. The method of claim 1 , further comprising:
storing the at least one attribute and the physical address in a translation look aside buffer (TLB).
3. The method of claim 2 , wherein the attribute cache comprises a greater number of entries than the TLB.
4. The method of claim 1 , wherein the attribute cache is operable to cache a first plurality of attributes that are time-consuming to obtain.
5. The method of claim 1 , further comprising:
determining whether the attribute cache is configured to speculatively load a plurality of attributes for a plurality of speculative physical addresses.
6. The method of claim 5 , further comprising:
responsive to the attribute cache being configured to speculatively load, accessing the logic to compute the plurality of attributes for the plurality of speculative physical addresses.
7. The method of claim 6 , further comprising:
storing the plurality of attributes and the plurality of speculative physical addresses in the attribute cache.
8. An apparatus comprising:
attribute logic operable to generate at least one attribute for a physical address in response to a translation look aside buffer (TLB) miss and an attribute cache miss; and
an attribute cache operable to store the least one attribute and the physical address.
9. The apparatus of claim 8 , wherein the attribute cache is configured to speculatively load a plurality of attributes for a plurality of speculative physical addresses.
10. The apparatus of claim 8 , wherein the attribute cache includes a plurality of attribute entries that are indexed with physical addresses.
11. The apparatus of claim 8 , wherein the at least one attribute is a translation bit that indicates whether a translation has been performed on a corresponding physical address.
12. The apparatus of claim 8 , wherein the at least one attribute is a cache status bit that indicates a cache status of a corresponding physical address.
13. The apparatus of claim 8 , further comprising a translation look aside buffer.
14. A non-transitory storage device comprising computer-executable instructions stored therein, the computer-executable instructions comprising:
instructions to access a logic to compute at least one attribute for a physical address in response to a translation look aside buffer (TLB) miss and an attribute cache miss; and
instructions to store the at least one attribute and the physical address in an attribute cache.
15. The non-transitory storage device of claim 14 , wherein the computer-executable instructions further comprise:
instructions to store the at least one attribute and the physical address in a translation look aside buffer (TLB).
16. The non-transitory storage device of claim 15 , wherein the attribute cache comprises a greater number of entries than the TLB.
17. The non-transitory storage device of claim 14 , wherein the attribute cache is operable to cache a first plurality of attributes that are time-consuming to obtain.
18. The non-transitory storage device of claim 14 , wherein the computer-executable instructions further comprise:
instructions to determine whether the attribute cache is configured to speculatively load a plurality of attributes for a plurality of speculative physical addresses.
19. The non-transitory storage device of claim 18 , wherein the computer-executable instructions further comprise:
instructions to access the logic to compute the plurality of attributes for the plurality of speculative physical addresses responsive to the attribute cache being configured to speculatively load.
20. The non-transitory storage device of claim 19 , wherein the computer-executable instructions further comprise:
instructions to store the plurality of attributes and the plurality of speculative physical addresses in the attribute cache.