Handling direct memory accesses
View Patent ↗Methods and systems for efficiently processing direct memory access requests coherently. An external agent requests data from the memory system of a computer system at a target address. A snoop cache determines if the target address is within an address range known to be safe for external access. If the snoop cache determines that the target address is safe, the external agent proceeds with the direct memory access. If the snoop cache does not determine if the target address is safe, then the snoop cache forwards the request on to the processor. After the processor resolves any coherency problems between itself and the memory system, the processor signals the external agent to proceed with the direct memory access. The snoop cache can determine safe address ranges from such processor activity. The snoop cache invalidates its safe address ranges by observing traffic between the processor and the memory system.
1. A method comprising:
receiving a target address;
determining said target address as safe if a cached data corresponding to said target address is the same as a data stored in a memory system; and
transmitting said target address to a processor for further processing if said target address is not safe.
2. The method as described by claim 1 , wherein said determining comprises:
accessing a storage medium comprising a safe address range to evaluate whether said target address is safe.
3. The method as described by claim 1 , further comprising:
storing said target address in a storage medium comprising a safe address range if said target address is safe.
4. The method as described by claim 2 , wherein said storage medium comprises a cache and a cache entry operable to hold safety information for at least two safe address ranges.
5. The method as described by claim 1 , wherein said determining comprises:
evaluating a safety of said target address for at least two block sizes.
6. The method as described by claim 1 , wherein said determining comprises:
evaluating said target address against an aligned first safe address range with a first granularity.
7. The method as described by claim 6 , wherein said determining comprises:
evaluating said target address against an aligned second safe address range with a second granularity.
8. A method of performing a direct memory access (DMA) operation comprising:
monitoring traffic and constructing safety information regarding a plurality of address ranges based on said monitoring;
receiving a request to perform a DMA operation involving a target address;
determining whether said target address is safe based on said safety information; and
transmitting said DMA operation for further processing if said target address is unsafe.
9. The method as described in claim 8 , wherein said safety information is stored within a cache memory.
10. The method as described in claim 8 further comprising:
resolving coherency problems if said target address is determined to be unsafe; and
in response to said resolving, allowing said DMA operation to occur.
11. The method as described in claim 8 , wherein said target address is determined to be safe if a cached data associated with said target address comprises same information as data stored in memory.
12. The method as described in claim 8 further comprising:
invalidating said safety information for said target address if data incoherency associated with said target address is detected.
13. The method as described in claim 8 further comprising:
allowing said DMA operation to occur if said target address is safe.
14. The method as described in claim 8 further comprising:
generating a signal by a processor responsive to said determining; and
validating said safety information as safe in response to said signal indicating that said target address is safe.
15. A system comprising:
a memory component; and
a snoop circuit for monitoring traffic associated with said memory component, wherein said snoop circuit is configured to construct safety information regarding a plurality of address ranges based on said monitoring, wherein said snoop circuit is further configured to determine whether a target address associated with a request for a direct memory access (DMA) operation is safe, and wherein said snoop circuit is further configured to transmit said request for further processing if said target address is determined to be unsafe.
16. The system as described by claim 15 , wherein said snoop circuit is further configured to allow said DMA operation to occur if said target address is safe.
17. The system as described by claim 15 , wherein said safety information is stored within a cache memory.
18. The system as described in claim 15 further comprising:
a processor configured to resolve coherency problems if said target address is unsafe, and wherein said processor is further configured to allow said DMA operation to occur responsive to said resolve.
19. The system as described in claim 15 , wherein said target address is determined to be safe if a cached data associated with said target address comprises same information as data stored in said memory component.
20. The system as described in claim 15 , wherein said snoop circuit is further configured to invalidate said safety information for said target address if data incoherency associated with said target address is detected.
21. A system comprising:
means for monitoring traffic and means for constructing safety information regarding a plurality of address ranges based on said monitoring;
means for receiving a request to perform a direct memory access (DMA) operation involving a target address;
means for determining whether said target address is safe based on said safety information; and
means for transmitting said DMA operation for further processing if said target address is unsafe.
22. The system as described in claim 21 , wherein said safety information is stored within a cache memory.
23. The system as described in claim 21 further comprising:
means for resolving coherency problems if said target address is determined to be unsafe; and
means for allowing said DMA operation to occur in response to said resolving.
24. The system as described in claim 21 , wherein said target address is determined to be safe if a cached data associated with said target address comprises same information as data stored in memory.
25. The system as described in claim 21 further comprising:
means for invalidating said safety information for said target address if data incoherency associated with said target address is detected.
26. The system as described in claim 21 further comprising:
means for allowing said DMA operation to occur if said target address is safe.
27. The system as described in claim 21 further comprising:
means for generating a signal by a processor responsive to said determining; and
means for validating said safety information as safe in response to said signal indicating that said target address is safe.