Saving power when in or transitioning to a static mode of a processor
View Patent ↗A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
1. A method comprising:
transitioning a processor to a reduced operation mode within a variable time allowed that varies based on a processor configuration; and
reducing a voltage to the processor by a value dependent on the variable time allowed, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode.
2. The method of claim 1 , wherein said transitioning comprises:
disabling a clock of the processor.
3. The method of claim 1 , wherein the voltage reduced by the value is sufficient to permit the processor to transition from the reduced operation mode to an operation mode within the variable time allowed.
4. The method of claim 1 , wherein the reduced operation mode is a deep sleep mode.
5. The method of claim 1 , wherein said transitioning comprises transitioning a voltage regulator from a first regulation mode to a second regulation mode, and wherein said reducing comprises generating the voltage by using the voltage regulator.
6. The method of claim 5 , wherein the voltage regulator comprises a feedback circuit coupled to an output terminal of the voltage regulator.
7. The method of claim 1 , wherein said transitioning comprises:
responsive to a stop clock signal, transitioning the processor to the reduced operation mode.
8. An apparatus comprising:
a processor configured to operate in a reduced operation mode; and
a circuit configured to reduce a voltage to the processor by a value dependent on a variable time allowed for the processor to transition to the reduced operation mode, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode, and wherein the variable time allowed varies based on a processor configuration.
9. The apparatus of claim 8 , wherein a clock of the processor is disabled in the reduced operation mode.
10. The apparatus of claim 8 , wherein the voltage reduced by the value is sufficient to permit the processor to transition from the reduced operation mode to an operation mode within the variable time allowed.
11. The apparatus of claim 8 , wherein the reduced operation mode is a deep sleep mode.
12. The apparatus of claim 8 , wherein the circuit comprises a voltage regulator, and wherein the voltage regulator comprises a feedback circuit coupled to an output terminal of the voltage regulator.
13. The apparatus of claim 12 , wherein the voltage regulator is configured to operate in a first regulation mode and in a second regulation mode.
14. The apparatus of claim 13 , wherein the voltage regulator generates the voltage while operating in the second regulation mode.
15. The apparatus of claim 8 , wherein the processor operates in the reduced operation mode in response to a stop clock signal.
16. A circuit comprising:
an input terminal;
an output terminal; and
a voltage regulator coupled to the input and output terminals, wherein the voltage regulator is configured to reduce a voltage to a processor by a value dependent on a variable time allowed for the processor to transition to a reduced operation mode, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode, and wherein the variable time allowed varies based on a processor configuration.
17. The circuit of claim 16 , wherein the voltage reduced by the value is sufficient to permit the processor to transition from the reduced operation mode to an operation mode within the variable time allowed.
18. The circuit of claim 16 , wherein the voltage regulator is configured to operate in a first regulation mode and in a second regulation mode.
19. The circuit of claim 18 , wherein the voltage regulator generates the voltage while operating in the second regulation mode.
20. The circuit of claim 16 , wherein the reduced operation mode is a deep sleep mode.
21. The circuit of claim 16 , wherein the voltage regulator includes a feedback circuit coupled to the output terminal.