Variable output charge pump circuit
View Patent ↗A drive frequency source with two selectable output frequencies connected to two charge pump arrays. A first array of basic charge pump units is connected to the first output frequency and a second array of basic charge pump units is connected to the output frequency. One or more of the basic charge pump units making up the aforementioned first and second charge pump arrays has an enable input allowing its output current contribution to be added or subtracted from the total array output. The output of the first array is coupled to a P-type substrate and the output of the second array is coupled to an N-well residing in the P-type substrate. A controller may be coupled to the drive frequency source for selecting the output frequencies, and an output monitor may be coupled between the array outputs and the controller to provide feedback.
1. A variable output charge pump circuit comprising:
a first array comprising a plurality of charge pump units coupled in parallel, said first array further comprising a first array common input and a first array common output, wherein each charge pump unit of said plurality of charge pump units of said first array comprises a respective enable input, said enable input for allowing a current contribution from a respective said charge pump to be added or subtracted to said first array variable common output;
a second array comprising a plurality of charge pump units coupled in parallel, said second array further comprising a second array common input and a second array common output; and
a clock divider operable to provide a plurality of selectable frequencies, said clock divider comprising a primary frequency input, a first selectable frequency output coupled to said first array common input, wherein said charge pump units of said first array are configured to switch at said first selectable frequency derived from said clock divider, and a second selectable frequency output coupled to said second array common input, wherein said charge pump units of said second array are configured to switch at said second selectable frequency derived from said clock divider.
2. The variable output charge pump circuit of claim 1 , wherein at least one charge pump unit of said second array does not comprise an enable input such that said charge pump is configured to be always operational and added to said second array common output.
3. The variable output charge pump circuit of claim 1 , wherein the nominal output ratios of charge pump units in said first array comprise a binary progression.
4. The variable output charge pump circuit of claim 1 , wherein the nominal outputs of the charge pump units in said first array are analogous.
5. The variable output charge pump circuit of claim 1 , wherein the number of charge pump units in said first array is different from the number of charge pump units in said second array.
6. The variable output charge pump circuit of claim 1 , wherein the frequencies of the selectable frequency outputs comprise a binary progression.
7. The variable output charge pump circuit of claim 1 , wherein the highest and lowest selectable frequencies have a ratio of 256 to 1.
8. A CMOS programmable variable output charge pump circuit comprising:
a charge pump controller comprising a first control signal and a second control signal;
a dual output charge pump circuit coupled to said charge pump controller, said dual output charge pump circuit comprising two charge pump arrays, said charge pump arrays comprising a plurality of charge pump units and wherein said first and said second control signals are coupled to said two charge pump arrays respectively;
an N-well coupled to a first output of said dual output charge pump circuit; and
a P-type substrate coupled to a second output of said dual output charge pump circuit.
9. The CMOS programmable variable output charge pump circuit of claim 8 , wherein said charge pump controller is a microprocessor.
10. The CMOS programmable variable output charge pump circuit of claim 9 , further comprising an inverter configured for biasing by said dual output charge pump circuit.
11. The CMOS programmable variable output charge pump circuit of claim 8 , further comprising an output monitor coupled between said charge pump controller and the outputs of said dual output charge pump circuit.
12. The CMOS programmable variable output charge pump circuit of claim 8 , wherein said first output is coupled to said N-well by a buried N-well.
13. The CMOS programmable variable output charge pump circuit of claim 8 , wherein said N-well comprises a functional transistor of said charge pump controller.
14. The CMOS programmable variable output charge pump circuit of claim 8 , wherein said dual output charge pump circuit comprises:
a first array of charge pump units coupled in parallel and coupled to said first output, wherein each charge pump unit of said first array of charge pumps comprises a respective internal enable input, said internal enable input for allowing a respective said charge pump to be added or subtracted to a common output of said first array;
a second array of charge pump units coupled in parallel and coupled to said second output; and
a clock divider comprising a primary frequency input, a first selectable frequency output coupled to said first array, and a second selectable frequency output coupled to said second array.
15. An integrated circuit comprising:
a microprocessor;
a charge pump controller;
a dual output charge pump circuit coupled to said charge pump controller wherein said dual output charge pump circuit comprises:
a first array of charge pump units coupled in parallel and coupled to said first output, wherein each charge pump unit of said first array of charge pumps comprises a respective internal enable input, said internal enable input for allowing a respective said charge pump to be added or subtracted to a common output of said first array;
a second array of charge pump units coupled in parallel and coupled to said second output; and
a clock divider comprising a primary frequency input, a first selectable frequency output coupled to said first array, wherein said charge pump units of said first array are configured to be switched at said first selectable frequency derived from said clock divider, and a second selectable frequency output coupled to said second array, wherein said charge pump units of said second array are configured to be switched at said second selectable frequency derived from said clock divider;
an N-well coupled to a first output of said a dual output charge pump circuit; and
a P-type substrate coupled to a second output of said a dual output charge pump circuit.
16. The integrated circuit of claim 15 , wherein said microprocessor comprises an inverter configured for biasing by said dual output charge pump circuit.
17. The integrated circuit of claim 15 , further comprising an output monitor coupled between said charge pump controller and the outputs of said dual output charge pump circuit.
18. The integrated circuit of claim 15 , wherein said first output is coupled to said N-well by a buried N-well.
19. The variable output charge pump circuit of claim 15 , wherein at least one charge pump unit of said second array does not comprise an enable input such that said charge pump is configured to be always operational and added to said second array common output.