IP Library Granted Patent US 7,180,322
Granted Patent B1
US 7,180,322 · App. 10/956,207 · Granted Feb 20, 2007

Closed loop feedback control of integrated circuits

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Quick Facts
Patent No.
US 7,180,322
App. No.
10/956,207
Granted
Feb 20, 2007
Kind
B1
Abstract

Systems and methods for closed loop feedback control of integrated circuits. In one embodiment, a plurality of controllable inputs to an integrated circuit is adjusted to achieve a predetermined value of a dynamic operating indicator of the integrated circuit. An operating condition of an integrated circuit is controlled via closed loop feedback based on dynamic operating indicators of the integrated circuit's behavior.

Claims (52)

1. A method of operating an integrated circuit, said method comprising:

measuring a dynamic operating indicator of said integrated circuit;

adjusting a plurality of controllable inputs to said integrated circuit to approach a predetermined value of said dynamic operating indicator of said integrated circuit.

2. A method as described in claim 1 further comprising accessing said predetermined value from a computer usable media.

3. A method as described in claim 2 further comprising periodically repeating said measuring and said adjusting.

4. A method as described in claim 1 wherein said plurality of controllable inputs comprises an operating voltage of said integrated circuit.

5. A method as described in claim 1 wherein said plurality of controllable inputs comprises a body bias voltage.

6. A method as described in claim 5 wherein said body bias voltage comprises a voltage applied to an n type metal oxide semiconductor device of said integrated circuit.

7. A method as described in claim 5 wherein said body bias voltage comprises a voltage applied to a p type metal oxide semiconductor device of said integrated circuit.

8. A method as described in claim 1 further comprising determining said predetermined value of a dynamic operating indicator of said integrated circuit.

9. A method as described in claim 8 further comprising storing said predetermined value of a dynamic operating indicator of said integrated circuit in a computer usable media.

10. A method as described in claim 2 wherein said dynamic operating indicator indicates a gate delay of said integrated circuit.

11. A method as described in claim 2 wherein said dynamic operating indicator indicates an off current of said integrated circuit.

12. A method as described in claim 2 wherein said dynamic operating indicator indicates a gate leakage of said integrated circuit.

13. A method as described in claim 2 wherein said dynamic operating indicator indicates a behavior of one type of device selected from the set of NMOS devices and PMOS devices of said integrated circuit.

14. A system for operating an integrated circuit, said system comprising:

circuitry for measuring a current dynamic operation indicator of said integrated circuit; and

a feedback loop coupled to said circuitry, said feedback loop for optimizing a dynamic operating indicator of said integrated circuit toward a predetermined value of said dynamic operating indicator by controlling a plurality of controllable inputs to said integrated circuit.

15. A system as described in claim 14 further comprising a computer usable media to store said predetermined value of said dynamic operating indicator.

16. A system as described in claim 14 wherein said plurality of controllable inputs comprises an operating voltage of said integrated circuit.

17. A system as described in claim 14 wherein said plurality of controllable inputs comprises a body bias voltage.

18. A system as described in claim 17 wherein said body bias voltage comprises a voltage applied to an n type metal oxide semiconductor device of said integrated circuit.

19. A system as described in claim 17 wherein said body bias voltage comprises a voltage applied to a p type metal oxide semiconductor device of said integrated circuit.

20. A system as described in claim 14 wherein said dynamic operating indicator indicates a gate delay of said integrated circuit.

21. A system as described in claim 14 wherein said dynamic operating indicator indicates an off current of said integrated circuit.

22. A system as described in claim 14 wherein said dynamic operating indicator indicates a gate leakage of said integrated circuit.

23. A system as described in claim 14 wherein said dynamic operating indicator indicates a behavior of one type of device selected from the set of NMOS devices and PMOS devices of said integrated circuit.

24. A microprocessor comprising:

a plurality of dynamic operating indicators for indicating operating conditions of said microprocessor;

a first computer usable media comprising a predetermined value for at least one of said plurality of dynamic operating indicators;

a second computer usable media comprising computer usable instructions which when executed on said microprocessor implement a method comprising:

accessing said predetermined value from said first computer usable media;

obtaining a measured record of at least one dynamic operation indicator; and

adjusting said operating voltage to said microprocessor until said measured record is near said predetermined value for said at least one of said plurality of dynamic operating indicators.

25. A microprocessor as described in claim 24 operable at a variety of voltages and frequencies.

26. A microprocessor as described in claim 24 operable to accept a variable voltage supply.

27. A microprocessor as described in claim 24 comprising a ring oscillator for measuring said at least one current dynamic operating indicator.

28. A computer system comprising:

a microprocessor;

a plurality of dynamic operating indicators for indicating operating conditions of said microprocessor;

a variable voltage supply to provide an operating voltage to said microprocessor;

a first computer usable media coupled to said microprocessor and comprising a predetermined value for at least one of said plurality of dynamic operating indicators;

a second computer usable media coupled to said microprocessor and comprising computer usable instructions which when executed on said microprocessor implement a method, said method comprising:

accessing said predetermined value from said first computer usable media; and

adjusting said operating voltage to said microprocessor to achieve said predetermined value for said at least one of said plurality of dynamic operating indicators.

29. A computer system as described in claim 28 wherein said microprocessor comprises at least one of said plurality of dynamic operating indicators.

30. A method as described in claim 1 wherein said predetermined value is a function.

31. A system for operating an integrated circuit, said system comprising:

circuitry for measuring a current dynamic operation indicator of said integrated circuit; and

a feedback loop coupled to said circuitry, said feedback loop for optimizing a function of a plurality of dynamic operating indicators of said integrated circuit toward a predetermined value of said function by controlling a plurality of controllable inputs to said integrated circuit.

32. A microprocessor as described in claim 24 wherein said predetermined value is a function.

33. A computer system as described in claim 28 wherein said predetermined value is a function.

Assignments (8)
CHANGE OF NAME Recorded Jan 27, 2022
From: FACEBOOK, INC.
To: META PLATFORMS, INC.
Reel/Frame 058871/0336 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2019
From: INTELLECTUAL VENTURES ASSETS 88 LLC
To: FACEBOOK, INC.
Reel/Frame 048136/0179 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2018
From: INTELLECTUAL VENTURES HOLDING 81 LLC
To: INTELLECTUAL VENTURES ASSETS 88 LLC
Reel/Frame 047014/0629 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 6, 2015
From: INTELLECTUAL VENTURES FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036797/0356 →
MERGER Recorded Sep 29, 2015
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036711/0160 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2009
From: TRANSMETA LLC
To: INTELLECTUAL VENTURE FUNDING LLC
Reel/Frame 023268/0771 →
MERGER Recorded Mar 26, 2009
From: TRANSMETA CORPORATION
To: TRANSMETA LLC
Reel/Frame 022454/0522 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2004
From: KONIARIS, KLEANTHES G.; BURR, JAMES B.
To: TRANSMETA CORPORATION
Reel/Frame 015869/0670 →