Method and system for caching attribute data for matching attributes with physical addresses

1. A computer-readable non-transitory storage device comprising computer-executable instructions stored therein, the computer-executable instructions for performing operations comprising:

accessing an attribute cache to obtain at least one attribute corresponding to a physical address in response to a translation look aside buffer (TLB) miss;

accessing a logic to compute the at least one attribute for the physical address in response to a miss during the accessing the attribute cache; and

storing the at least one attribute and the physical address within the attribute cache.

2. The computer-readable storage device of claim 1 , further comprising:

storing the at least one attribute and the physical address within a translation look aside buffer (TLB).

3. The computer-readable storage device of claim 2 , wherein the attribute cache comprises a greater number of entries than the TLB.

4. The computer-readable storage device of claim 1 , wherein the attribute cache is operable to cache a first plurality of attributes that are time-consuming to obtain.

5. The computer-readable storage device of claim 1 , further comprising:

determining whether the attribute cache is configured for speculatively loading of a plurality of attributes for a plurality of speculative physical addresses.

6. The computer-readable storage device of claim 5 , further comprising:

responsive to the attribute cache being configured for speculatively loading, accessing the logic to compute the plurality of attributes for the plurality of speculative physical addresses.

7. The computer-readable storage device of claim 6 , further comprising:

storing the plurality of attributes and the plurality of speculative physical addresses within the attribute cache.

8. A cache memory, comprising:

means for storing attributes that correspond to physical addresses, wherein the means for storing is accessed in response to a translation look aside buffer (TLB) miss; and

means for receiving a physical address and generating at least one attribute for the physical address to store in the means for storing.

9. The cache memory of claim 8 , wherein the means for storing is configured to support speculative attribute lookups to obtain a plurality of attribute entries for a plurality of speculative physical addresses.

10. The cache memory of claim 8 , further comprising:

means for supporting an attribute lookup to obtain an attribute entry if the attribute entry is unavailable in the means for storing.

11. The cache memory of claim 8 , wherein the means for storing includes a plurality of attribute entries that are indexed with physical addresses.

12. The cache memory of claim 8 , wherein the at least one attribute is a translation bit that indicates whether a translation has been performed on a corresponding physical address.

13. The cache memory of claim 8 , wherein the at least one attribute is a cache status bit that indicates a cache status of a corresponding physical address.

14. A system, comprising:

a processing device; and

a cache memory coupled to the processing device, wherein the cache memory includes:

an attribute cache operable to store attributes that correspond to physical addresses, wherein the attribute cache is accessed in response to a translation look aside buffer (TLB) miss; and

attribute logic operable to receive a physical address and operable to generate at least one attribute for the physical address to store in the attribute cache.

15. The system of claim 14 , further comprising a translation look aside buffer (TLB) coupled to the processing device.

16. The system of claim 15 , wherein the attribute cache is in a parallel arrangement with respect to the TLB and the attribute logic.

17. The system of claim 15 , wherein the attribute cache is in a serial arrangement with respect to the TLB and the attribute logic.

18. The system of claim 15 , wherein the attribute cache comprises a greater number of entries than the TLB.

19. The system of claim 14 , further comprising:

a system memory coupled to the processing device.

20. The system of claim 14 , further comprising:

a north bridge coupled to the processing device; and

a south bridge coupled to the processing device.