Fractional biasing of semiconductors
View Patent ↗A method and system of fractional biasing of semiconductors. A small negative voltage is applied to the back of a semiconductor wafer or device. An operating voltage is applied to the semiconductor. Operating characteristics of the semiconductor are enhanced by application of a fractional bias.
1. A method of operating a semiconductor device comprising:
applying an operating voltage to said semiconductor device; and
applying a fractional negative voltage to a second surface of said semiconductor device.
2. The method of claim 1 wherein said fractional negative voltage is applied by a wafer test machine.
3. The method of claim 1 wherein said fractional negative voltage is applied to said semiconductor device within a semiconductor package.
4. The method of claim 1 wherein said fractional negative voltage is produced by said semiconductor device.
5. The method of claim 1 wherein said fractional negative voltage is less than about 50 millivolts in magnitude.
6. A method comprising:
supplying a positive voltage to a top surface of a semiconductor wafer;
testing said semiconductor wafer;
responsive to a failure of said testing, applying a fractional negative voltage to a bottom side of a substrate of said wafer; and
retesting said semiconductor wafer with said negative voltage applied to said bottom side.
7. The method of claim 6 further comprising marking said wafer with a first pass indicator in response to passing said testing.
8. The method of claim 6 further comprising marking said wafer with a second pass indicator in response to passing said retesting.
9. The method of claim 7 and further comprising binning said wafer based on said first pass indicator.
10. The method of claim 6 further comprising testing said wafer at least a third time responsive to a failure of said retesting.
11. The method of claim 6 further comprising rejecting said wafer as defective responsive to a failure of said retesting.
12. The method of claim 6 further comprising repeating said testing, applying and retesting for a plurality of wafers.