Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions
View Patent ↗Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.
1. A semiconductor device having a surface, comprising:
a first well region of a first conductivity formed beneath said surface;
a second well region of said first conductivity formed beneath said surface; and
a conductive sub-surface region of said first conductivity formed beneath said first and second well regions, wherein said conductive sub-surface region is diagonally positioned relative to said first and second well regions such that a first conductive boundary is formed between said first well region and said conductive sub-surface region and a second conductive boundary is formed between said second well region and said conductive sub-surface region to provide a sub-surface conductive path between said first and second well regions.
2. The semiconductor device as recited in claim 1 wherein said conductive sub-surface region has an N-type doping.
3. The semiconductor device as recited in claim 2 wherein said first well region has an N-type doping, and wherein said second well region has an N-type doping.
4. The semiconductor device as recited in claim 3 wherein said first well region includes a p-type MOSFET (metal oxide semiconductor field effect transistor), and wherein said second well region includes a p-type MOSFET.
5. The semiconductor device as recited in claim 3 further comprising a second conductive sub-surface region of said first conductivity formed beneath said first and second well regions, wherein said second conductive sub-surface region is parallel to said conductive sub-surface region.
6. The semiconductor device as recited in claim 1 wherein said conductive sub-surface region has a P-type doping.
7. The semiconductor device as recited in claim 6 wherein said first well region has a P-type doping, and wherein said second well region has a P-type doping.
8. The semiconductor device as recited in claim 7 wherein said first well region includes an N-type MOSFET (metal oxide semiconductor field effect transistor), and wherein said second well region includes an N-type MOSFET.
9. The semiconductor device as recited in claim 1 wherein said conductive sub-surface region has a strip shape.
10. The semiconductor device as recited in claim 1 wherein said conductive sub-surface region routes a body-bias voltage to said first and second well regions.
11. The semiconductor device as recited in claim 1 wherein said conductive sub-surface region and said first well region form an angle that is approximately 45 degrees.
12. The semiconductor device as recited in claim 1 wherein said conductive sub-surface region and said second well region form an angle that is approximately 45 degrees.
13. A semiconductor device having a surface, comprising:
a first well region of a first conductivity formed beneath said surface;
a second well region of said first conductivity formed beneath said surface; and
a plurality of conductive sub-surface regions of said first conductivity each formed beneath said first and second well regions, wherein said plurality of conductive sub-surface regions are arranged into a sub-surface mesh structure, and wherein said sub-surface mesh structure is diagonally positioned relative to said first and second well regions such that a first plurality of conductive boundaries are formed between said first well region and said sub-surface mesh structure and a second plurality of conductive boundaries are formed between said second well region and said sub-surface mesh structure to provide a plurality of sub-surface conductive paths between said first and second well regions.
14. The semiconductor device as recited in claim 13 wherein each conductive sub-surface region has an N-type doping.
15. The semiconductor device as recited in claim 14 wherein said first well region has an N-type doping, and wherein said second well region has an N-type doping.
16. The semiconductor device as recited in claim 15 wherein said first well region includes a p-type MOSFET (metal oxide semiconductor field effect transistor), and wherein said second well region includes a p-type MOSFET.
17. The semiconductor device as recited in claim 13 wherein each conductive sub-surface region has a P-type doping.
18. The semiconductor device as recited in claim 17 wherein said first well region has a P-type doping, and wherein said second well region has a P-type doping.
19. The semiconductor device as recited in claim 18 wherein said first well region includes an N-type MOSFET (metal oxide semiconductor field effect transistor), and wherein said second well region includes an N-type MOSFET.
20. The semiconductor device as recited in claim 13 wherein each conductive sub-surface region has a strip shape.
21. The semiconductor device as recited in claim 13 wherein said sub-surface mesh structure routes a body-bias voltage to said first and second well regions.
22. The semiconductor device as recited in claim 13 wherein said sub-surface mesh structure is rotated approximately 45 degrees relative to said first well region.
23. The semiconductor device as recited in claim 13 wherein said sub-surface mesh structure is rotated approximately 45 degrees relative to said second well region.
24. The semiconductor device as recited in claim 13 wherein an area of said sub-surface mesh structure 490 is equally divided between said conductive sub-surface regions of said first conductivity and a gap area.
25. The semiconductor device as recited in claim 13 further comprising a second sub-surface layer of a second conductivity formed beneath said sub-surface mesh structure, wherein a gap between adjacent parallel conductive sub-surface regions is sufficiently wide to avoid pinching-off a conductive path to said second sub-surface layer.
26. A semiconductor device having a surface, comprising:
a first well region of a first conductivity formed beneath said surface;
a second well region of said first conductivity formed beneath said surface;
a region of a second conductivity formed beneath said surface; and
a conductive sub-surface region of said first conductivity formed beneath said first and second well regions and said region, wherein said conductive sub-surface region is diagonally positioned relative to said first and second well regions and said region such that a first conductive boundary is formed between said first well region and said conductive sub-surface region and a second conductive boundary is formed between said second well region and said conductive sub-surface region to provide a sub-surface conductive path between said first and second well regions without isolating said region.
27. The semiconductor device as recited in claim 26 wherein said conductive sub-surface region has an N-type doping.
28. The semiconductor device as recited in claim 27 wherein said first well region has an N-type doping, and wherein said second well region has an N-type doping.
29. The semiconductor device as recited in claim 28 wherein said first well region includes a p-type MOSFET (metal oxide semiconductor field effect transistor), and wherein said second well region includes a p-type MOSFET.
30. The semiconductor device as recited in claim 29 wherein said region has a P-type doping, and wherein said region includes an N-type MOSFET (metal oxide semiconductor field effect transistor).
31. The semiconductor device as recited in claim 26 wherein said conductive sub-surface region has a P-type doping.
32. The semiconductor device as recited in claim 31 wherein said first well region has a P-type doping, and wherein said second well region has a P-type doping.
33. The semiconductor device as recited in claim 32 wherein said first well region includes an N-type MOSFET (metal oxide semiconductor field effect transistor), and wherein said second well region includes an N-type MOSFET.
34. The semiconductor device as recited in claim 33 wherein said region has an N-type doping, and wherein said region includes a P-type MOSFET (metal oxide semiconductor field effect transistor).
35. The semiconductor device as recited in claim 26 wherein said conductive sub-surface region has a strip shape.
36. The semiconductor device as recited in claim 26 wherein said conductive sub-surface region routes a body-bias voltage to said first and second well regions.
37. The semiconductor device as recited in claim 26 wherein said conductive sub-surface region and said first well region form an angle that is approximately 45 degrees.
38. The semiconductor device as recited in claim 26 wherein said conductive sub-surface region and said second well region form an angle that is approximately 45 degrees.
39. The semiconductor device as recited in claim 26 wherein said conductive sub-surface region and said region form an angle that is approximately 45 degrees.