Method and system for elastic signal pipelining

1. A method for configuring a signal path within a digital integrated circuit, comprising:

transmitting an output from a first module;

receiving the output at a second module;

conveying the output from the first module to the second module by using a configurable signal path, wherein the configurable signal path is variable by selectively including at least one latch, and wherein the first module, the second module, and the configurable signal path use a common clock for a single time domain.

2. The method of claim 1 , wherein a control module is used to selectively include the at least one latch onto the configurable signal path.

3. The method of claim 2 , wherein the control module is configured to include the at least one latch onto the configurable signal path to increase a clock frequency of the configurable signal path.

4. The method of claim 3 , wherein the control module is configured to include a variable number of latches onto the configurable signal path to accommodate a variable increase of the clock frequency of the configurable signal path.

5. The method of claim 1 , wherein the digital integrated circuit comprises a logic unit having a plurality of logic modules, and wherein a corresponding plurality of configurable signal paths couple the logic modules into a pipeline.

6. The method of claim 1 , wherein the latch comprises a storage element and a multiplexer configured to selectively couple the storage element to the configurable signal path in accordance with a control signal.

7. The method of claim 1 , wherein the first module comprises a first portion of a cache memory and the second module comprises a second portion of the cache memory.

8. A digital integrated circuit having a configurable signal path, comprising:

a first module configured to transmit an output;

a second module configured to receive the output;

a configurable signal path for conveying the output from the first module to the second module, wherein the configurable signal path is variable by selectively including at least one latch, and wherein the first module, the second module, and the configurable signal path use a common clock comprising a single time domain.

9. The digital integrated circuit of claim 8 , wherein a control module operates with a software based algorithm to dynamically include the at least one latch onto the configurable signal path.

10. The digital integrated circuit of claim 9 , wherein the control module is configured to include the at least one latch onto the configurable signal path to increase a clock frequency of the configurable signal path.

11. The digital integrated circuit of claim 10 , wherein the control module is configured to include a variable number of latches onto the configurable signal path to accommodate a variable increase of the clock frequency of the configurable signal path.

12. The digital integrated circuit of claim 8 , wherein the digital integrated circuit comprises a logic unit having a plurality of logic modules, and wherein a corresponding plurality of configurable signal paths couple the logic modules into a pipeline.

13. The method of claim 8 , wherein the first module comprises a first portion of a cache memory and the second module comprises a second portion of the cache memory.

14. A method for configuring a signal path within a digital integrated circuit, comprising:

transmitting an output from a first module;

receiving the output at a second module;

selectively including at least one storage element onto a configurable signal path, wherein a control module is used to selectively include the at least one storage element onto the configurable signal path;

conveying the output from the first module to the second module by using the configurable signal path, wherein the first module, the second module, and the configurable signal path use a common clock comprising a single time domain.

15. The method of claim 14 , wherein a control module is configured to remove a variable number of storage elements from the configurable signal path to accommodate a variable decrease of the clock frequency of the configurable signal path.

16. The method of claim 14 , wherein the digital integrated circuit comprises a cache memory.

17. The method of claim 14 , wherein the digital integrated circuit comprises a logic unit having a plurality of logic modules, and wherein a corresponding plurality of configurable signal paths couple the logic modules into a pipeline.

18. The method of claim 14 , wherein a software based algorithm is used to dynamically include the at least one storage element onto the configurable signal path to increase a clock frequency of the configurable signal path.

19. A circuit comprising configurable signal path circuit for implementing a configurable signal path to convey an output from a first module to a second module, wherein the configurable signal path is variable by selectively including at least one latch, and wherein the first module, the second module, and the configurable signal path circuit use a common clock comprising a single time domain.

20. The circuit of claim 19 , further comprising a control module for operating in accordance with an algorithm to dynamically include the at least one latch onto the configurable signal path.

21. The circuit of claim 20 , wherein the control module is configured to include the at least one latch onto the configurable signal path to increase a clock frequency of the configurable signal path.

22. The circuit of claim 20 , wherein the control module is configured to include a variable number of latches onto the configurable signal path to accommodate a variable increase of the clock frequency of the configurable signal path.