IP Library Granted Patent US 6,930,534
Granted Patent B1
US 6,930,534 · App. 10/439,659 · Granted Aug 16, 2005

Temperature compensated integrated circuits

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Quick Facts
Patent No.
US 6,930,534
App. No.
10/439,659
Granted
Aug 16, 2005
Kind
B1
Abstract

A method and system of temperature compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of temperature compensation.

Claims (37)

1. A ring oscillator integrated circuit comprising:

an odd number of inverter stages coupled in a ring configuration, each of said inverter stages comprising:

first, second, third, fourth, fifth and sixth transistor devices;

wherein said first, second, fourth and fifth transistor devices are coupled in series via their source and drain terminals;

wherein gate terminals of said first, second, fourth and fifth transistor devices are coupled together;

wherein said third and sixth transistor devices are coupled in series between said source of said second transistor device and said drain of said fourth transistor device;

wherein gate terminals of said third and sixth transistor devices are coupled together;

wherein said gate and drain terminals of said third transistor device are coupled to said drain terminal of said second transistor device; and

wherein a common coupling of gate terminals of said first, second, fourth and fifth transistor devices form an input terminal for said inverter stage.

2. A temperature compensated NAND integrated circuit comprising:

first, second, third and fourth temperature compensated transfer resistor circuits, each of said temperature compensated transfer resistor circuits comprising:

first and second transistor devices coupled in series drain to source;

a third transistor device coupled in parallel with said second transistor device;

wherein gate terminals of said first and second transistor devices are coupled together;

wherein gate and drain terminals of said third transistor device are coupled together;

wherein said first and second temperature compensated transfer resistor circuits taking separate inputs are coupled together in parallel;

wherein said third and fourth temperature compensated transfer resistor circuits taking separate inputs are coupled together in series; and

wherein outputs of said first, second and third temperature compensated transfer resistor circuits are coupled together.

3. The temperature compensated NAND integrated circuit of claim 2 wherein a frequency response characteristic of said temperature compensated NAND integrated circuit shows substantially less variation with temperature than a frequency response characteristic of a similar temperature compensated NAND integrated circuit absent said third transistor devices.

4. The temperature compensated NAND integrated circuit of claim 2 wherein said first and second temperature compensated transfer resistor circuits comprise p-type carriers.

5. The temperature compensated NAND integrated circuit of claim 2 wherein said third and fourth temperature compensated transfer resistor circuits comprise n-type carriers.

6. The temperature compensated NAND integrated circuit of claim 2 embodied in a microprocessor.

7. The temperature compensated NAND integrated circuit of claim 6 embodied in a computer system.

8. A temperature compensated NOR integrated circuit comprising:

first, second, third and fourth temperature compensated transfer resistor circuits, each of said temperature compensated transfer resistor circuits comprising:

first and second transistor devices coupled in series drain to source;

a third transistor device coupled in parallel with said second transistor device;

wherein gate terminals of said first and second transistor devices are coupled together;

wherein gate and drain terminals of said third transistor device are coupled together;

wherein said first and second temperature compensated transfer resistor circuits taking separate inputs are coupled together in parallel;

wherein said third and fourth temperature compensated transfer resistor circuits taking separate inputs are coupled together in series; and

wherein outputs of said first, second and third temperature compensated transfer resistor circuits are coupled together.

9. The temperature compensated NOR integrated circuit of claim 8 wherein a frequency response characteristic of said temperature compensated NOR integrated circuit shows substantially less variation with temperature than a frequency response characteristic of a similar temperature compensated NOR integrated circuit absent said third transistor devices.

10. The temperature compensated NOR integrated circuit of claim 8 wherein said third and fourth temperature compensated transfer resistor circuits comprise p-type carriers.

11. The temperature compensated NOR integrated circuit of claim 8 wherein said first and second temperature compensated transfer resistor circuits comprise n-type carriers.

12. The temperature compensated NOR integrated circuit of claim 8 embodied in a microprocessor.

13. The temperature compensated NOR integrated circuit of claim 12 embodied in a computer system.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 036711 FRAME: 0160. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 6, 2015
From: INTELLECTUAL VENTURES FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036797/0356 →
MERGER Recorded Sep 29, 2015
From: INTELLECTUAL VENTURE FUNDING LLC
To: INTELLECTUAL VENTURES HOLDING 81 LLC
Reel/Frame 036711/0160 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2009
From: TRANSMETA LLC
To: INTELLECTUAL VENTURE FUNDING LLC
Reel/Frame 023268/0771 →
MERGER Recorded Mar 26, 2009
From: TRANSMETA CORPORATION
To: TRANSMETA LLC
Reel/Frame 022454/0522 →