Body-bias voltage routing structures
View Patent ↗Body-bias voltage routing structures. In an embodiment, doped well structures distribute body biasing voltages to a plurality of body biasing wells of an integrated circuit.
1. A semiconductor device comprising:
at least two conductive regions of a first conductivity formed beneath a surface of the semiconductor device, wherein the at least two conductive regions are configured to route a body-bias voltage, and wherein the at least two conductive regions do not contact one another; and
at least one metal structure formed above the surface, wherein the at least one metal structure is coupled to the at least two conductive regions.
2. The semiconductor device of claim 1 , wherein each conductive region has an N-type doping.
3. The semiconductor device of claim 1 , wherein each conductive region has a P-type doping.
4. The semiconductor device of claim 1 , wherein each conductive region has a strip shape.
5. The semiconductor device of claim 1 , wherein the metal structure has a metal wire shape.
6. The semiconductor device of claim 1 , wherein the at least two conductive regions do not reach the surface.
7. A semiconductor device having a surface, the semiconductor device comprising:
at least two conductive regions of a first conductivity, wherein each conductive region is formed beneath the surface, and wherein the at least two conductive regions form a first sub-surface structure operable to route a body-bias voltage;
at least two other conductive regions of the first conductivity, wherein each other conductive region is formed beneath the surface, wherein the other conductive regions form a second sub-surface structure operable to route the body-bias voltage and wherein the first and second sub-surface structures are physically separate; and
at least one metal structure formed above the surface, wherein the at least one metal structure couples the first sub-surface structure and the second sub-surface structure via at least two tap contacts.
8. The semiconductor device of claim 7 , wherein each conductive region has an N-type doping.
9. The semiconductor device of claim 7 , wherein each conductive region has a P-type doping.
10. The semiconductor device of claim 7 , wherein at least one of the conductive regions has a strip shape.
11. The semiconductor device of claim 7 , wherein the metal structure has a metal wire shape.
12. The semiconductor device of claim 7 , wherein the conductive structures do not reach the surface.
13. A semiconductor device having a surface, the semiconductor device comprising:
at least two conductive regions of a first conductivity formed beneath a surface of the semiconductor device, wherein the at least two conductive regions are configured to route a body-bias voltage, and wherein the at least two conductive regions are non-continuous; and
at least one conductive structure above the surface that is coupled to the at least two conductive regions.
14. The semiconductor device of claim 13 , wherein each conductive region has an N-type doping.
15. The semiconductor device of claim 13 , wherein each conductive region has a P-type doping.
16. The semiconductor device of claim 13 , wherein each conductive region has a strip shape.
17. The semiconductor device of claim 13 , wherein the conductive structure is a polysilicon wire.
18. The semiconductor device of claim 13 , wherein the conductive structure is a diffusion wire.
19. The semiconductor device of claim 13 , wherein the conductive structure is a silicide wire.
20. The semiconductor device of claim 13 , wherein each of the conductive regions has a continuous sub-surface layer shape.