Method and system for caching attribute data for matching attributes with physical addresses
View Patent ↗A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.
1. A method comprising:
responsive to an attribute cache miss associated with a first physical address, determining at least one attribute for the first physical address and at least one attribute for a second physical address that is speculatively selected; and
storing the at least one attribute for the first physical address and the at least one attribute for the second physical address in an attribute cache.
2. The method of claim 1 , wherein the attribute cache miss occurs before a translation look aside buffer (TLB) miss associated with the second physical address.
3. The method of claim 2 , further comprising:
responsive to the TLB miss associated with the second physical address, accessing the attribute cache to obtain the at least one attribute for the second physical address.
4. The method of claim 1 , wherein the attribute cache miss occurs before a translation look aside buffer (TLB) requests the second physical address.
5. The method of claim 4 , further comprising:
responsive to a request for the second physical address from the TLB, accessing the attribute cache to obtain the at least one attribute for the second physical address.
6. The method of claim 1 , further comprising:
responsive to a translation look aside buffer (TLB) miss associated with the second physical address, accessing the attribute cache to obtain the at least one attribute for the second physical address.
7. The method of claim 1 , further comprising:
storing the at least one attribute for the first physical address in a translation look aside buffer (TLB).
8. An apparatus comprising:
logic operable to determine at least one attribute for a first physical address that is speculatively selected and at least one attribute for a second physical address responsive to an attribute cache miss associated with the second physical address; and
an attribute cache operable to store the at least one attribute for the first physical address and the at least one attribute for the second physical address.
9. The apparatus of claim 8 , wherein the attribute cache miss occurs before a translation look aside buffer (TLB) miss associated with the first physical address.
10. The apparatus of claim 9 , wherein the attribute cache is further operable to provide the at least one attribute for the first physical address responsive to the TLB miss associated with the first physical address.
11. The apparatus of claim 8 , wherein the attribute cache miss occurs before a translation look aside buffer (TLB) requests the first physical address.
12. The apparatus of claim 11 , wherein the attribute cache is further operable to provide the at least one attribute for the first physical address responsive to a request for the first physical address from the TLB.
13. The apparatus of claim 8 , wherein the attribute cache is further operable to provide the at least one attribute for the first physical address responsive to a translation look aside buffer (TLB) miss associated with the first physical address.
14. The apparatus of claim 8 , further comprising:
a translation look aside buffer (TLB) operable to store the at least one attribute for the first physical address and the at least one attribute for the second physical address.
15. A non-transitory storage device comprising computer-executable instructions stored therein, the computer-executable instructions comprising:
instructions to determine at least one attribute for a first physical address that is speculatively selected and at least one attribute for a second physical address responsive to an attribute cache miss associated with the second physical address; and
instructions to store the at least one attribute for the first physical address and the at least one attribute for the second physical address in an attribute cache.
16. The non-transitory storage device of claim 15 , wherein the attribute cache miss occurs before a translation look aside buffer (TLB) miss associated with the second physical address.
17. The non-transitory storage device of claim 16 , wherein the computer-executable instructions further comprise:
instructions to access the attribute cache to obtain the at least one attribute for the second physical address responsive to the TLB miss associated with the second physical address.
18. The non-transitory storage device of claim 15 , wherein the attribute cache miss occurs before a translation look aside buffer (TLB) requests the second physical address.
19. The non-transitory storage device of claim 18 , wherein the computer-executable instructions further comprise:
instructions to access the attribute cache to obtain the at least one attribute for the second physical address responsive to a request for the second physical address from the TLB.
20. The non-transitory storage device of claim 15 , wherein the computer-executable instructions further comprise:
instructions to access the attribute cache to obtain the at least one attribute for the second physical address responsive to a translation look aside buffer (TLB) miss associated with the second physical address.