Three dimensional integrated circuits
View Patent ↗A programmable integrated circuit (IC), comprising: a programmable logic circuit configured by a first control signal coupled to a gate electrode of a transistor in the logic circuit; and a first plurality of read only memory (ROM) elements capable of coupling to the first control signal, wherein a said first ROM elements is selected to couple by one or more decode signals, and wherein the first ROM elements store a plurality of user specifications.
1. A mask configurable semiconductor device, comprising:
a programmable logic circuit having a high impedance node; and
an output of a multiplexer coupled to the high impedance node to configure the programmable logic circuit, the multiplexer including:
two or more inputs; and
one or more control signals, the control signals uniquely coupling a said input to the output of the multiplexer; and
a plurality of read only memory elements (ROMs), a said ROM element coupled to each of said inputs to multiplexer, wherein the ROM elements are positioned substantially above or below the programmable logic circuit.
2. The device of claim 1 , wherein a said ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage.
3. The device of claim 2 , wherein a said ROM element is customized during the fabrication process, said customization comprised of:
identifying power or ground supply voltage connection to program the programmable logic circuit to said user specification, and
customizing at least one mask in the fabrication process to provide said power or ground supply voltage connection.
4. The device of claim 3 , wherein said at least one custom mask comprises a metal mask or a thru-hole mask in a multi-metal fabrication process.
5. The device of claim 1 , wherein interconnect and routing signals are positioned above or below the ROM elements.
6. The device of claim 1 , wherein interconnect and routing signals are positioned above and below the ROM elements.
7. The device of claim 1 , wherein the multiplexer is positioned above the programmable logic circuit.
8. A programmable semiconductor device, comprising:
a plurality of programmable pass-gate logic elements constructed on a semiconductor substrate layer, each said pass-gate logic elements comprising a gate electrode; and
a plurality of multiplexers, a said multiplexer coupled to the gate electrode of a said pass-gate logic element; and
a plurality of read only memory (ROM) elements, two or more of said ROM elements coupled to the said multiplexer to selectively couple one of the ROM elements to program the pass-gate logic element to one of two or more user specifications, wherein the ROM elements are positioned substantially above or below the semiconductor substrate layer.
9. The device of claim 8 , wherein a said pass-gate logic element is configured by a digital input signal received at the gate electrode, and wherein the digital input signal is generated by a said ROM element.
10. The device of claim 8 , wherein a said pass-gate logic element comprises one of a semiconductor substrate transistor and a semiconductor thin-film transistor.
11. The device of claim 8 , wherein a said ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage.
12. The device of claim 8 , wherein the two or more ROM elements are configured during the fabrication process, said configuration comprised of:
identifying power or ground supply voltage connection for each of said ROM bits to program the logic circuit to each of said user specifications, and
customizing at least one mask in the fabrication process to provide said power or ground supply voltage connections.
13. The device of claim 12 , wherein said at least one custom mask comprises a metal mask or a thru-hole mask in a multi-metal fabrication process.
14. The device of claim 8 , wherein interconnect and routing signals are positioned above or below the ROM elements.
15. The device of claim 8 , wherein interconnect and routing signals are positioned above and below the multiplexer.
16. The device of claim 8 , wherein the multiplexer is coupled to a decode signal to selectively couple one of said two or more ROM elements to couple to the gate electrode to program the logic element.
17. A programmable integrated circuit (IC), comprising:
a programmable logic circuit configured by a first control signal coupled to a gate electrode of a transistor in the logic circuit; and
a first plurality of read only memory (ROM) elements capable of coupling to the first control signal, wherein a said first ROM elements is selected to couple by one or more decode signals, and wherein the first ROM elements store a plurality of user specifications.
18. The IC of claim 17 , further comprising:
a programmable metal interconnect configured by a second control signal coupled to a configurable element in the programmable metal interconnect; and
a second plurality of read only memory (ROM) elements capable of coupling to the second control signal, wherein a said second ROM elements is selected to couple by one or more decode signals, and wherein the second ROM elements store a plurality of user specifications.
19. The IC of claim 17 , wherein a said ROM element comprises a metal wire coupled to a power supply voltage or a metal wire coupled to a ground supply voltage as identified by one of said user specifications.
20. The IC of claim 18 , wherein the one or more decode signals are common to both programmable logic circuit and the programmable metal interconnect to chose one specification to configure the IC from the plurality of ROM coded user specifications.