Methods for fabricating fuse programmable three dimensional integrated circuits

1. A method of fabricating a field programmable integrated circuit comprised of:

constructing a semiconductor device comprising a fuse circuit to customize the logic content of a programmable logic circuit; and

attaching said semiconductor device in a detachable lid package, wherein the fuses are customized in the field by detaching the lid and blowing one or more fuse elements.

2. The method of claim 1 , further comprised of:

providing a custom hard-wire pattern in lieu of the fuse circuit, wherein the programmable logic circuit timing is identical between the fuse circuit and hard-wire options.

3. The method of claim 1 , further comprised of:

fabricating digital circuits and said programmable logic circuit on a semiconductor substrate; and

fabricating interconnect and routing layers above the digital circuits and the programmable logic circuit; and

fabricating said fuse circuit above the interconnect and routing layers.

4. The method of claim 1 , further comprised of:

coupling each programmable node in the programmable logic circuit to two fuse elements; and

coupling one of said fuse elements to a logic one rail, and coupling the other of said fuse elements to a logic zero rail, wherein customizing the fuse circuit comprises blowing one or the other of said fuse elements.

5. The method of claim 4 , wherein the fuse elements are programmed by one of thermal, electrical, optical, mechanical, magnetic, chemical and vibrational means.

6. The method of claim 4 , wherein the fuse elements are programmed by an optical laser beam.

7. The method of claim 4 , wherein the fabrication process sequence further comprises:

forming NMOS and PMOS transistors on a semiconductor substrate;

depositing above the NMOS and PMOS transistors an interconnect and routing structure comprising one or more metallization modules, each said module further comprised of:

depositing and polishing an inter metal dielectric layer;

forming inter metal contact plugs; and

depositing metal and forming metal tracks;

depositing an isolation dielectric material and performing CMP to isolate the interconnect and routing structure;

forming contact plugs to contact the top metal layer in the interconnect structure;

depositing one or more metal layers comprising a fuse metal layer with desired characteristics for rapid and reliable fuse blow;

depositing an isolation dielectric material; and

applying a pad mask and etching pads.

8. A method of forming a programmable semiconductor device comprised of:

fabricating digital circuits comprising a programmable logic circuit on a substrate;

fabricating an interconnect and routing structure substantially above the digital circuits; and

fabricating a programmable fuse circuit above the routing structure to program said programmable logic circuit, wherein the fuse circuit is programmed to store binary data values.

9. The method of claim 8 , further comprised of:

coupling each programmable node in the programmable logic circuit to two fuse elements; and

coupling one of said fuse elements to a logic one rail, and coupling the other of said fuse elements to a logic zero rail;

wherein, programming the fuse circuit comprises blowing one or the other of said fuse elements.

10. The method of claim 8 , wherein the fuse elements are blown by one of thermal, electrical, optical, mechanical, magnetic, chemical and vibrational means.

11. The method of claim 8 , wherein the fuse elements are blown by an optical laser beam.

12. The method of claim 8 , wherein the digital circuits and interconnect and routing structure fabrication utilizes a logic process sequence.

13. The method of claim 12 , wherein the logic process sequence further comprises:

forming a P-type substrate;

creating a twin well;

developing a shallow trench isolation;

performing a sacrificial oxide;

generating a PMOS Vt mask and implant;

generating a NMOS Vt mask and implant;

developing gate oxidation;

depositing gate poly (GP);

applying the GP mask and etch;

applying an LDN mask and implant;

applying an LDP mask and implant;

depositing a spacer oxide and etching the spacer oxide;

depositing Nickel;

performing RTA anneal—Ni salicidation (S/D/G regions & interconnect)

etching to remove unreacted Nickel;

depositing ILD oxide and performing CMP;

applying a C 1 mask and etch;

forming a W plug and performing CMP;

depositing M 1 ;

applying a M 1 mask & etch; and

performing back end metallization.

14. The method of claim 8 , wherein the programmable fuse fabrication process sequence further comprises:

depositing an isolation dielectric material and performing CMP to isolate the interconnect and routing structure;

forming contact plugs to contact the top metal layer in the interconnect structure to the fuse elements;

depositing one or more metal layers comprising a fuse metal layer with desired characteristics for rapid and reliable fuse blow;

depositing an isolation dielectric material above the fuse metal; and

applying a pad mask and etching pads.

15. The method of claim 8 , wherein a given fuse blow pattern in the fuse circuit has a corresponding mask configurable conductive pattern in lieu of said fuse circuit, both of which identically program said programmable logic circuit.

16. The method of claim 15 , wherein one or more of the digital circuit characteristics comprises a timing characteristic substantially unchanged by the programmable option.

17. The method of claim 8 , further comprised of using a bit stream of digital logic one and logic zero generated by a computer aided design automation tool during the place and route phase of custom logic placement and timing optimization to generate the fuse blow pattern.

18. A method of fabricating a programmable integrated circuit comprised of:

fabricating a packaged semiconductor device comprising only a laser fuse circuit as the top most metal layer to customize the logic content of a programmable logic circuit.

19. The method of claim 18 , wherein each programmable node in the logic circuit is coupled to two laser fuse elements, one fuse element coupled to a power bus and the other fuse element coupled to a ground bus.

20. The method of claim 18 , wherein the package comprises a detachable lid to remove the lid in the field and blow the fuse elements with an optical laser beam.