Configuration circuits for programmable logic devices

1. A configuration circuit in a programmable logic device, comprising:

a first voltage and a second voltage at a lower level than said first voltage; and

a control signal coupled to a capacitive node to program a programmable logic circuit, wherein said control signal comprises a digital high and digital low signal levels; and

a first configurable element comprising an on state and an off state coupled between the first voltage and the control signal; and

a second configurable element comprising an on state and an off state coupled between the second voltage and the control signal; and

a programmable means to configure one of:

the first element to on state and the second element to off state to couple the first voltage to the control signal; and

the second element to on state and the first element to off state to couple the second voltage to the control signal;

wherein, a very low conducting current through the on configurable element is adequate to charge the capacitive node to said digital high or digital low signal levels.

2. The circuit of claim 1 , wherein the configurable elements comprises one of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, thin-film memory cells, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, electro-magnetic elements, carbon nano-tube elements, optical elements, mask programmable elements or any other memory element.

3. The circuit of claim 1 , wherein the configurable element comprises a low on current in said on state, and a lower off current in said off state.

4. The circuit of claim 1 , wherein the on and off configurable element comprises an on and off current respectively, wherein the ratio of said on current to off current is greater than 10, and preferably greater than 100, and more preferably greater than 1000.

5. The circuit of claim 1 , wherein each capacitive node comprises one or more of:

an input to one or more inverters; and

a gate terminal to one or more transistors; and

a capacitive load of one or more storage devices.

6. The circuit of claim 1 , wherein:

the configurable elements are further comprised of random access memory (RAM) elements; and

the programmable means is further comprised of providing a decode method for a user to access each configurable element to alter the element between said on and off states.

7. The circuit of claim 1 , wherein the programmable logic circuit comprises a first and a second noise margin voltage level, and wherein the control signal further comprises:

the digital high signal level in a range of first voltage level to first voltage level minus the first noise margin voltage level; and

the digital low signal level in a range of second voltage level to second voltage level plus the second noise margin voltage level;

wherein, the programmable logic circuit has no performance degradation from the digital signal level range.

8. The circuit of claim 1 , wherein an on first configurable element can be replaced by a metal wire coupled to the first voltage level with no change to programmable logic circuit performance.

9. The circuit of claim 1 , wherein an on second configurable element can be replaced by a metal wire coupled to the second voltage level with no change to programmable logic circuit performance.

10. The circuit of claim 1 , wherein the first voltage level is at system power voltage level, and wherein the second voltage level is at system ground voltage level.

11. A semiconductor device, comprised of:

a programmable logic circuit comprising a plurality of programmable elements, each element further comprising a capacitive node, wherein a control signal received at the capacitive node programs the element; and

a configuration circuit comprising a plurality of configurable elements to generate the control signals, wherein each of the control signals is generated by:

a first configurable element comprising an on state and an off state coupled between a first voltage and the control signal; and

a second configurable element comprising an on state and an off state coupled between a second voltage at a lower level than said first voltage and the control signal; and

a programmable means to configure one of:

the first element to on state and the second element to off state to couple the first voltage to the control signal; and

the second element to on state and the first element to off state to couple the second voltage to the control signal;

wherein, a low conducting current through the on configurable element is adequate to charge the capacitive node to said first or second voltage levels.

12. The device of claim 11 , wherein the configurable elements comprises one of fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, thin-film memory cells, EPROM cells, EEPROM cells, flash cells, ferro-electric elements, electro-chemical elements, electro-magnetic elements, carbon nano-tube elements, optical elements, mask programmable elements or any other memory element.

13. The device of claim 11 , wherein the configurable element comprises a low on current in the range of 10 pico-amps to 10 micro-amps in said on state, and a lower off current in said off state.

14. The device of claim 11 , wherein the on and off configurable element comprises an on and off current respectively, wherein the ratio of said on current to off current is greater than 10, and preferably greater than 100, and more preferably greater than 1000.

15. The device of claim 11 , wherein each capacitive node comprises one or more of:

an input to one or more inverters; and

a gate terminal to one or more transistors; and

a capacitive load of one or more storage devices.

16. The device of claim 11 , wherein:

the configurable elements are further comprised of random access memory (RAM) elements; and

the programmable means is further comprised of providing a decode method for a user to access each configurable element to alter the element between said on and off states.

17. The device of claim 11 , wherein the programmable logic circuit comprises a first margin voltage level and a second margin voltage level, and wherein the control signal further comprises:

a digital high signal level in a range of first voltage level to first voltage level minus the first margin voltage level; and

a digital low signal level in a range of second voltage level to second voltage level plus the second margin voltage level;

wherein, the programmable logic circuit has no performance degradation from the digital signal level range.

18. The device of claim 11 , wherein an on first configurable element can be replaced by a metal wire coupled to the first voltage level, and wherein an on second configurable element can be replaced by a metal wire coupled to the second voltage level with no change to programmable logic circuit performance.

19. The device of claim 11 , wherein the first voltage level is at system power voltage level, and wherein the second voltage level is at system ground voltage level.

20. A semiconductor device, wherein:

a programmable logic circuit is configured by a control signal received at a capacitive node in the circuit, wherein the control signal is further generated by one of:

a low conducting current pull-up configurable element configured to couple the control signal to a power supply voltage; and

a low conducting current pull-down configurable element configured to couple the control signal to a ground supply voltage;

wherein, the low conducting current charge the capacitive node to either the power or ground voltage levels.