Pads and pin-outs in three dimensional integrated circuits
View Patent ↗A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.
1. A plurality of semiconductor devices, comprising:
a programmable device including a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer including a plurality of input/output characteristics and a plurality of pads in an arrangement; and
a hard-wired device including a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer.
2. The plurality of semiconductor devices of claim 1 , wherein the first programmable layer, the memory layer, and the first pad layer are positioned in a stack arrangement.
3. The plurality of semiconductor devices of claim 1 , wherein the second programmable layer, the hard-wire layer, and the second pad layer are positioned in a stack arrangement.
4. The plurality of semiconductor devices of claim 1 , wherein the first pad layer is identical to the second pad layer.
5. The plurality of semiconductor devices of claim 1 , wherein the first programmable layer is identical to the second programmable layer.
6. The plurality of semiconductor devices of claim 1 , wherein the hard-wire layer comprises a pattern of metal layers.
7. The plurality of semiconductor devices of claim 1 , wherein the input/output characteristics of the first pad layer are identical to input/output characteristics of the second pad layer.
8. An apparatus, comprising:
a pad interface circuit operable with a programmable device and further operable with a hard-wired device, wherein the programmable device and the hard-wired device are interchangeable, and wherein:
the programmable device includes a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer operable with the pad interface circuit; and
the hard-wired device includes a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer and operable with the pad interface circuit.
9. The apparatus of claim 8 , wherein the first programmable layer, the memory layer, and the first pad layer are positioned in a stack arrangement.
10. The apparatus of claim 8 , wherein the second programmable layer, the hard-wire layer, and the second pad layer are positioned in a stack arrangement.
11. The apparatus of claim 8 , wherein the first pad layer is identical to the second pad layer.
12. The apparatus of claim 8 , wherein the first programmable layer is identical to the second programmable layer.
13. The apparatus of claim 8 , wherein the hard-wire layer comprises a pattern of metal layers.
14. The apparatus of claim 8 , wherein input/output characteristics of the first pad layer are identical to input/output characteristics of the second pad layer.
15. An apparatus, comprising:
a peripheral device operable with a programmable device, further operable with a hard-wired device, and including an interface configuration, wherein the programmable device and the hard-wired device are interchangeable, and wherein:
the programmable device includes a first programmable layer, a memory layer operable to program the first programmable layer with a logical functionality, and a first pad layer operable with the interface configuration; and
the hard-wired device includes a second programmable layer with common design relative to the first programmable layer, a hard-wire layer operable to hard-wire the second programmable layer with the logical functionality, and a second pad layer with common design relative to the first pad layer and operable with the interface configuration.
16. The apparatus of claim 15 , wherein the first programmable layer, the memory layer, and the first pad layer are positioned in a stack arrangement.
17. The apparatus of claim 15 , wherein the second programmable layer, the hard-wire layer, and the second pad layer are positioned in a stack arrangement, and wherein the hard-wire layer comprises a pattern of metal layers.
18. The apparatus of claim 15 , wherein the first pad layer is identical to the second pad layer.
19. The apparatus of claim 15 , wherein the first programmable layer is identical to the second programmable layer.
20. The apparatus of claim 15 , wherein input/output characteristics of the first pad layer are identical to input/output characteristics of the second pad layer.