Methods for fabricating three dimensional integrated circuits

1. A method of forming a semiconductor device, comprising:

fabricating digital circuits comprising a programmable logic circuit on a substrate;

selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and

fabricating an interconnect and routing structure substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern;

wherein the conductive pattern fabrication option utilizes a logic process sequence and the selective memory circuit fabrication option utilizes a thin-film transistor (TFT) process sequence inserted to said logic process sequence, wherein the logic process sequence further comprises:

forming a P-type substrate;

creating a twin well;

developing a shallow trench isolation;

performing a sacrificial oxide;

generating a PMOS Vt mask and implant;

generating a NMOS Vt mask and implant;

developing gate oxidation;

depositing gate poly (GP);

applying the GP mask and etch;

applying an LDN mask and implant;

applying an LDP mask and implant;

depositing a spacer oxide and etching the spacer oxide;

depositing Nickel; performing RTA anneal—Ni salicidation (S/DIG regions & interconnect) etching to remove unreacted Nickel;

depositing ILD oxide and performing CMP;

applying a Cl mask and etch;

forming a W plug and performing CMIP;

depositing Ml;

applying a Ml mask & etch; and

performing back end metallization.

2. A method of forming a semiconductor device, comprising:

fabricating digital circuits comprising a programmable logic circuit on a substrate:

selectively fabricating either a memory circuit or a conductive pattern substantially above the digital circuits to program said programmable logic circuit; and

fabricating an interconnect and routing structure substantially above the digital circuits and memory circuits to connect digital circuits and one of the memory circuit or the conductive pattern;

wherein the conductive pattern fabrication option utilizes a logic process sequence and the selective memory circuit fabrication option utilizes a thin-film transistor (TFT) process sequence inserted to said logic process sequence, wherein the thin-film transistor (TFT) process sequence further comprises:

depositing amorphous poly-1 (P1);

performing P1 mask & etch;

applying NMOS Vt mask & P−implant;

applying PMOS Vt mask & N−implant; depositing Gox;

applying buried contact mask & etch;

depositing amorphous poly-2 (P2);

applying P2 mask & etch;

applying LDN mask & N−implant;

applying LDP mask & P−implant;

depositing Gox;

depositing a spacer oxide and etching the spacer oxide;

applying N+mask & implanting NMOS G/S/D;

applying P+mask & implanting PMOS G/S/D;

depositing Nickel;

salicidizing the Nickel on the G/SID regions & interconnect;

performing RTA anneal—P1 and P2 re-crystallization;

depositing ILD oxide & CMP;

applying C 2 mask & etch; and

forming a W plug & CMIP.

3. A method to fabricate a monolithic programmable logic device, comprising:

constructing digital circuits comprising a programmable logic circuit on a substrate; and constructing a non-planar configuration circuit above the digital circuits to program said programmable circuit, said configuration circuit being:

either a memory circuit deposited to store configuration data to fabricate a field programmable gate array (FPGA) device, or a conductive pattern deposited to hard-wire configuration data to fabricate an application specific integrated circuit (ASIC) device;

wherein the FPGA and the ASIC have substantially matching timing characteristics; and

wherein constructing the configuration circuit is further comprised of constructing one of SRAM, DRAM, EEPROM, EPROM, Flash, ferro-electric, electro-magnetic, electro-chemical, fuse-link, anti-fuse capacitor, carbon filament, mask-programmable ROM or any other programmable memory element that can be configured to store a logic zero or a logic one.

4. The method of claim 3 , wherein constructing the configuration conductive pattern is further comprised of constructing a mask-programmable read only memory comprising hard-wires connected to either a power-supply or a ground-supply to store a logic one or a logic zero respectively.