Semiconductor devices fabricated with different processing options

1. A semiconductor device to provide a configurable functionality, the device fabricated with two different fabricating options comprising:

a first fabricating option wherein one or more logic transistors are fabricated utilizing a first set of masks and a first process sequence, and wherein a user configurable memory element to program said logic transistors is fabricated utilizing a second set of masks; and

a second fabricating option wherein the logic transistors are fabricated utilizing the first set of masks and the first process sequence, and a mask configurable memory element to program said logic transistors is fabricated utilizing a third set of masks, the third set having fewer masks than the second set.

2. The device of claim 1 , wherein the user configurable memory element and the mask configurable memory element identically program the logic transistors.

3. The device of claim 1 , wherein utilizing the second set of masks requires a second process sequence, and wherein utilizing the third set of masks requires a third process sequence, the third process sequence having fewer processing steps than the second process sequence.

4. The device of claim 1 , wherein the first fabricating option comprises fabricating field programmable interconnects utilizing a fourth set of masks, and wherein the second fabricating option comprises fabricating mask programmable interconnects utilizing a fifth set of masks, the fourth and fifth sets having one or more common masks.

5. The device of claim 1 , wherein the first fabricating option comprises fabricating field programmable interconnects utilizing a fourth set of masks, and wherein the second fabricating option comprises fabricating mask programmable interconnects utilizing a fifth set of masks, the fourth and fifth sets differ by at least one mask.

6. The device of claim 4 , wherein utilizing the fourth set of masks requires a fourth process sequence, and wherein utilizing the fifth set of masks requires a fifth process sequence, the fourth process sequence identical to the fifth process sequence.

7. The device of claim 5 , wherein utilizing the fourth set of masks requires a fourth process sequence, and wherein utilizing the fifth set of masks requires a fifth process sequence, the fourth process sequences identical to the fifth process sequence.

8. The device of claim 1 , wherein the user configurable memory element is one of electrical-fuse links, laser-fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, Flash cells, Carbon nano-tubes, Electro-Chemical cells, Electro-Mechanical cells, Optical cells, Electro-Magnetic cells and Ferro-Electric cells.

9. The device of claim 1 , wherein the mask configurable memory element is one of a metal connection and a metal disconnection.

10. A semiconductor device to provide a configurable functionality, the device fabricated with two different fabricating options comprised of:

a first fabricating option comprising:

masks and processing steps to fabricate transistors; and

a first process sequence to fabricate a user configurable memory element above the transistors; and

a second fabricating option comprising:

said masks and said processing steps to fabricate transistors; and

a second process sequence to fabricate a mask configurable memory element above the transistors, the second process sequence comprising fewer processing steps than the first process sequence.

11. The device of claim 10 , wherein the user configurable memory element is one of electrical-fuse links, laser-fuse links, antifuse capacitors, SRAM cells, DRAM cells, metal optional links, EPROM cells, EEPROM cells, Flash cells, Carbon nano-tubes, Electro-Chemical cells, Electro-Mechanical cells, Optical cells, Electro-Magnetic cells and Ferro-Electric cells.

12. The device of claim 10 , wherein the mask configurable memory element is one of a metal connection and a metal disconnection.

13. The device of claim 10 , wherein the processing steps to fabricate transistors comprises a logic process sequence to construct transistors on a semiconductor substrate.

14. The device of claim 10 , wherein the first process sequence utilizes a first set of masks, and the second process sequence utilizes a second set of masks, the second set comprising fewer masks than the first set.

15. The device of claim 10 , wherein the first fabricating option comprises fabricating field programmable interconnects utilizing a third process sequence, and wherein the second fabricating option comprises fabricating mask programmable interconnects utilizing a fourth process sequence, the third and fourth process sequences having the same processing steps.

16. The device of claim 15 , wherein the third process sequence utilizes a third set of masks and the fourth fabricating option utilizes a fourth set of masks, the fourth and third sets having at least one different mask.

17. The device of claim 16 , wherein at least one mask in the second fabricating option differs from masks in the first fabricating option and provides wire connections coupled to a power bus or a ground bus to hard-wire a user memory pattern in the first fabricating option.

18. A method to make a semiconductor device, comprising:

providing a first fabricating option providing a plurality of user configurations to configure the device functionality to form a user configurable device; and

providing a second fabricating option to form a custom device that hard-masks a functional configuration, the second option comprising a plurality of common masks and fewer processing steps compared to first fabricating option.

19. The method of claim 18 , wherein the first fabricating option comprises fabricating a user configurable memory element.

20. The method of claim 18 , wherein the second fabricating option comprises fabricating a mask configurable memory element.