Depopulated programmable logic array
View Patent ↗A programmable logic array (PLA) in accordance with the invention achieves a maximum amount of depopulation of programmable connections while still implementing a logic function and maintaining flexibility for future reprogramming. In addition, a PLA in accordance with the invention can be built so that no matter what functionality is programmed, performance characteristics for the device are maintained. Further, a PLA in accordance with the invention does not require a regular array structure.
1. An integrated circuit comprising:
a programmable logic array (PLA) depopulated to include programmable connections only where required to implement certain known functionality and selectively minimally repopulated to accommodate future programming of other functionality.
2. The integrated circuit of claim 1 , wherein:
the PLA programmed with the known functionality has certain performance characteristics, and wherein the PLA programmed with other functionality has the same performance characteristics.
3. The integrated circuit of claim 1 , wherein:
the programmable connections include a storage device and a logic gate;
the PLA includes product terms and sum terms formed with gate trees.
4. The integrated circuit of claim 3 , wherein:
the storage device is one of a latch or a flip-flop; and
the logic gate is an OR gate.
5. The integrated circuit of claim 3 , wherein:
the storage device is one of a latch or a flip-flop; and
the logic gate is a multiplexer.
6. The integrated circuit of claim 1 , wherein:
the programmable connections include a pair of storage devices and a multiplexer.
7. The integrated circuit of claim 1 , wherein the PLA includes:
an AND array with a first type of programmable connection; and
an OR array with a second type of programmable connection.
8. The integrated circuit of claim 1 , wherein the PLA includes:
an AND array with programmable connections that each include a pair of storage devices and a multiplexer; and
an OR array with programmable connections that each include only one storage device and a logic gate.
9. The integrated circuit of claim 1 , wherein the PLA includes:
programmable connections for shared terms, spare terms, and complemented terms.
10. An integrated circuit comprising:
a programmable logic array (PLA) having a depopulated array that includes programmable connections only where required to implement certain known functionality and selectively minimally repopulated to accommodate future programming of other functionality.
11. The integrated circuit of claim 10 , wherein the depopulated array is an AND array.
12. The integrated circuit of claim 10 , wherein the depopulated array is an OR array.
13. A programmable logic array (PLA) comprising:
an AND array that includes a first type of programmable connection; and
an OR array that includes a second type of programmable connection;
wherein the first type of programmable connection includes a pair of storage devices and a multiplexer; and
wherein the second type of programmable connection includes only one storage device and a logic gate.
14. An integrated circuit comprising:
a programmable logic array (PLA) having a depopulated array that includes programmable connections only where required to implement certain known functionality, wherein the PLA includes:
programmable connections that include a storage device and a logic gate; and
product terms and sum terms formed with gate trees.
15. An integrated circuit comprising:
a programmable logic array (PLA) having a depopulated array that includes programmable connections only where required to implement certain known functionality, wherein the PLA includes programmable connections that include:
a pair of storage devices; and
a multiplexer.
16. An integrated circuit comprising:
a programmable logic array (PLA) having a depopulated array that includes programmable connections only where required to implement certain known functionality, wherein the PLA includes:
an AND array that includes programmable connections that each include a pair of storage devices and a multiplexer; and
an OR array that includes programmable connections that each include only one storage device and a logic gate.