IP Library Assignment 037451/0611
Patent Assignment
Reel/Frame 037451/0611

Merger

Recorded: 2016-01-06 Pages: 37
Assignor
Assignee
CALLAHAN CELLULAR L.L.C.
2711 CENTERVILLE RD, SUITE 400, WILMINGTON, DELAWARE, 19808
Covered Properties (35)
Function Block Architecture for Gate Array
Patent: 6,014,038 →
Application: 08/821,475 →
Asic Routing Architecture
Patent: 6,242,767 →
Application: 08/966,946 →
Method and Apparatus for Controlling and Observing Data in a Logic Block-Based Asic
Patent: 6,223,313 →
Application: 08/985,790 →
Methods and Apparatuses for Binning Partially Completed Integrated Circuits Based Upon Test Results
Patent: 6,133,582 →
Application: 09/079,016 →
Design Information Memory for Configurable Integrated Circuits
Patent: 6,498,361 →
Application: 09/140,087 →
One-Mask Customizable Phase-Locked Loop
Patent: 6,770,949 →
Application: 09/144,489 →
Methods and Apparatuses for Binning Partially Completed Integrated Circuits Based Upon Test Results
Patent: 6,399,400 →
Application: 09/272,470 →
Function Block Architecture for Gate Array
Patent: 6,690,194 →
Application: 09/414,697 →
Programmable Logic Array Embedded in Mask-Programmed Asic
Patent: 6,694,491 →
Application: 09/512,783 →
Asic Routing Architecture with Variable Number of Custom Masks
Patent: 6,613,611 →
Application: 09/747,129 →
Depopulated Programmable Logic Array
Patent: 7,055,125 →
Application: 09/827,015 →
Publication: US 2002/0059555
Programmable Logic Array Embedded in Mask-Programmed Asic
Patent: 6,769,109 →
Application: 09/877,170 →
Publication: US 2002/0010903
Function Block Architecture with Variable Drive Strengths
Patent: 6,696,856 →
Application: 10/020,469 →
Asic Routing Architecture
Patent: 6,885,043 →
Application: 10/051,237 →
Publication: US 2003/0155587
Method and Apparatus for Controlling and Observing Data in a Logic Block-Based Asic
Patent: 6,611,932 →
Application: 10/056,686 →
Publication: US 2002/0073369
Method and Apparatus for Built-in Self-Test of Logic Circuits with Multiple Clock Domains
Patent: 6,861,867 →
Application: 10/093,767 →
Publication: US 2003/0169070
High Speed Differential Receiver
Patent: 6,680,626 →
Application: 10/161,931 →
Publication: US 2003/0227299
Modular Array Defined by Standard Cell Logic
Patent: 7,770,144 →
Application: 10/447,465 →
Publication: US 2004/0243966
Asic Customization with Predefined via Mask
Patent: 7,102,237 →
Application: 10/447,466 →
Depopulated Programmable Logic Array
Patent: 6,804,812 →
Application: 10/458,892 →
Publication: US 2003/0212979
Function Block Architecture for Gate Array and Method for Forming an Asic
Patent: 6,954,917 →
Application: 10/460,343 →
Publication: US 2003/0214324
Implementing Programmable Logic Array Embedded in Mask - Programmed Asic
Patent: 7,043,713 →
Application: 10/640,171 →
Publication: US 2004/0049759
Asic Customization with Predefined via Mask
Patent: 7,648,912 →
Application: 11/277,253 →
Increased Effective Flip-Flop Density in a Structured Asic
Patent: 7,461,365 →
Application: 11/456,219 →
Methods and Systems for Placement
Patent: 7,653,884 →
Application: 11/684,522 →
Publication: US 2007/0150846
Methods and Systems for Placement
Patent: 7,669,160 →
Application: 11/744,758 →
Publication: US 2007/0204252
Mutable Cells for Use in Integrated Circuits
Patent: 7,840,927 →
Application: 11/953,048 →
Incremental Relative Slack Timing Force Model
Patent: 7,814,451 →
Application: 11/967,179 →
Publication: US 2008/0216040
Timing Driven Force Directed Placement Flow
Patent: 7,752,588 →
Application: 11/967,180 →
Publication: US 2008/0216038
Node Spreading via Artificial Density Enhancement to Reduce Routing Congestion
Patent: 7,921,392 →
Application: 11/967,184 →
Publication: US 2008/0216039
Tunneling as a Boundary Congestion Relief Mechanism
Patent: 7,921,393 →
Application: 11/967,185 →
Publication: US 2008/0216025
Methods and Systems for Placement and Routing
Patent: 8,332,793 →
Application: 12/301,456 →
Publication: US 2009/0254874
Transparent Test Method and Scan Flip-Flop
Patent: 8,122,413 →
Application: 12/303,938 →
Publication: US 2010/0169856
Increased Effective Flip-Flop Density in a Structured Asic
Patent: 8,176,458 →
Application: 12/325,629 →
Publication: US 2009/0293035
Modular Array Defined by Standard Cell Logic
Patent: 8,504,950 →
Application: 12/842,670 →
Publication: US 2010/0299648
Related Assignments (6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 3, 2020
From: CALLAHAN CELLULAR L.L.C.
To: INTELLECTUAL VENTURES ASSETS 154 LLC
Reel/Frame 051464/0389 →
Assignment of Assignor's Interest Jan 4, 2020
From: INTELLECTUAL VENTURES ASSETS 158 LLC
To: HANGER SOLUTIONS, LLC
Reel/Frame 051486/0425 →
Assignment of Assignor's Interest Jan 27, 2020
From: INTELLECTUAL VENTURES ASSETS 154 LLC
To: LIBERTY PATENTS LLC
Reel/Frame 051709/0805 →
Assignment of Assignor's Interest Jan 28, 2020
From: CALLAHAN CELLULAR L.L.C.
To: INTELLECTUAL VENTURES ASSETS 158 LLC
Reel/Frame 051727/0155 →
Assignment of Assignor's Interest May 14, 2021
From: HANGER SOLUTIONS, LLC
To: FOOTHILLS IP LLC
Reel/Frame 056246/0533 →
Assignment of Assignor's Interest Apr 6, 2022
From: HANGER SOLUTIONS, LLC
To: TUMBLEWEED HOLDINGS LLC
Reel/Frame 059620/0066 →