Modular array defined by standard cell logic
View Patent ↗Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design.
1. A method comprising:
forming, on a wafer, at least one interconnect layer and a plurality of function blocks, wherein each function block includes a plurality of primitive cells, wherein each of the primitive cells comprises logic including a plurality of devices, wherein the at least one interconnect layer, circuitry of at least one of the function blocks, and circuitry of at least one of the primitive cells are fixedly defined by at least one component from a pre-existing library of standard cell logic, and wherein said forming is performed prior to receipt of a custom circuit design to be implemented using the plurality of function blocks, the plurality of primitive cells, and the at least one interconnect layer to thereby permit prefabrication of the plurality of function blocks; and
interconnecting, prior to receipt of the custom circuit design, at least some of the plurality of primitive cells to each other by at least one interconnect in the at least one interconnect layer, and leaving disconnected, prior to receipt of the custom circuit design, the plurality of function blocks from each other.
2. The method of claim 1 , further comprising determining, prior to receipt of the custom circuit design, placement of the plurality of function blocks based, at least in part, on a predicted relationship among the plurality of function blocks.
3. The method of claim 2 , further comprising arranging, prior to receipt of the custom circuit design, the plurality of function blocks and the plurality of primitive cells according to the respective predicted relationships.
4. The method of claim 3 , wherein said arranging comprises arranging the plurality of function blocks in an array.
5. The method of claim 3 , wherein respective logic of each of the plurality of function blocks is identical.
6. The method of claim 3 , wherein said arranging comprises arranging the plurality of primitive cells in rows in respective ones of the plurality of function blocks.
7. The method of claim 3 , wherein said arranging comprises arranging a plurality of pins to form a plurality of inputs and outputs for each of the plurality of function blocks.
8. The method of claim 7 , wherein said arranging comprises arranging the plurality of inputs and outputs to form a regular grid.
9. The method of claim 1 , wherein said forming comprises defining the circuitry for the primitive cells such that logic for each of the plurality of primitive cells for a particular function block is unique with respect to logic for other ones of the plurality of primitive cells for the particular function block.
10. The method of claim 1 , wherein said forming comprises arranging a plurality of pins according to a predicted relationship among the plurality of function blocks.
11. The method of claim 10 , wherein said arranging comprises routing the plurality of pins into a regular grid according to the predicted relationship.
12. The method of claim 10 , wherein said arranging comprises placing the plurality of pins according to the predicted relationship.