Function block architecture for gate array and method for forming an asic
View Patent ↗A method for forming an application specific integrated circuit, comprises receiving a circuit design for the application specific integrated circuit from a designer; performing an initial place and route layout of the circuit design which leaves a group of buffer modules unused, based upon a partially predesigned integrated circuit, in which the partially predesigned integrated circuit includes a plurality of logic modules and a plurality of buffer modules uniformly distributed amongst the logic modules; evaluating load and timing characteristics for the initial place and route layout of the circuit design; and integrating buffer modules from the group of unused buffer modules into the circuit design, based on the load and timing characteristics evaluated. A gate array, for forming the application specific integrated circuit in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers.
1. A method for forming an application specific integrated circuit, comprising:
receiving a circuit design for said application specific integrated circuit from a designer;
performing an initial place and route layout of said circuit design based upon a partially predesigned integrated circuit, said partially predesigned integrated circuit including a plurality of logic modules and a plurality of buffer modules, said buffer modules uniformly distributed amongst said logic modules, where said initial place and route layout leaves a group of buffer modules unused;
evaluating load and timing characteristics for said initial place and route layout of said circuit design; and
based upon said load and timing characteristics, integrating buffer modules from said group of unused buffer modules into said circuit design.
2. The method of claim 1 , wherein the steps of performing, evaluating and integrating are done using software.
3. The method of claim 1 , wherein:
evaluating load and timing characteristics includes evaluating fanout characteristics; and
integrating buffer modules includes inserting a buffer module wherever recommended fanout characteristics are exceeded.
4. The method of claim 1 , wherein:
evaluating load and timing characteristics includes evaluating conductor length; and
integrating buffer modules includes inserting a buffer module wherever recommended conductor length is exceeded.
5. The method of claim 1 , wherein:
evaluating load and timing characteristics includes evaluating hold times; and
integrating buffer modules includes inserting a buffer module wherever hold times are inadequate.
6. The method of claim 1 , wherein each of said logic modules includes circuitry configurable to perform any of a plurality of functions, including combinational and sequential functions, and wherein each buffer module includes at least one buffer.
7. The method of claim 6 , wherein said plurality of logic modules are arranged in an array.