Mutable cells for use in integrated circuits
View Patent ↗An integrated circuit implementation methodology uses mutable cells, e.g. cells that are capable of being personalized for use as one of a plurality of resource types. For example, a mutable cell is designed to have a component layout and a set of lower-layer internal connections compatible with both a design of a flip-flop, and a design of a pair of multiplexers. Independent customizations of the mutable cell, using higher layers of interconnect, efficiently use the cell as a flip-flop or as a pair of multiplexers. Use of mutable cells in an integrated circuit advantageously enables a set of predefined lower-layer photomask, such as for a predefined base array, to be efficiently shared among different applications. In some embodiments, a Simultaneous Dynamical Integration (SDI) Electronic Design Automation (EDA) flow advantageously uses mutable cells, such as to balance demand for resources against supply thereof.
1. A method comprising:
analyzing, by a computing apparatus, a placement of devices of at least a portion of a netlist of an integrated circuit, wherein the placement is in accordance with a first allocation of resources;
comparing, by the computing apparatus, a number of non-mutable elements of the resources of the first allocation to a number of mutable elements of the resources of the first allocation;
adding, by the computing apparatus, at least one additional non-mutable element to the first allocation if the number of mutable elements is greater than the number of non-mutable elements; and
formulating, by the computing apparatus, a second allocation of the resources by mutating, based at least in part on a result of said analyzing, comparing, and adding, a resource element of a first type to form a resource element of a second type.
2. The method of claim 1 , wherein at least one of the first type or the second type is a sequential logic resource.
3. The method of claim 1 , wherein at least one of the first type or the second type is a flip-flop resource.
4. The method of claim 1 , wherein the first type is a flip-flop resource and the second type is a combination logic resource.
5. The method of claim 1 , wherein the first type is a resource having a first drive strength and the second type is a resource having a second drive strength greater than the first drive strength.
6. The method of claim 1 , wherein said analyzing comprises analyzing a global placement of the devices.
7. The method of claim 1 , wherein said analyzing comprises analyzing a detailed placement of the devices.
8. The method of claim 1 , further comprising manufacturing, at least in part, the integrated circuit.
9. A non-transitory computer-readable medium having stored thereon, computer-executable instructions that, in response to execution by a computing apparatus, cause the computing apparatus to perform operations including:
analyzing a placement of devices of at least a portion of a netlist of an integrated circuit, wherein the placement is in accordance with a first allocation of resources;
comparing, by the computing apparatus, a number of non-mutable elements of the resources of the first allocation to a number of mutable elements of the resources of the first allocation;
adding, by the computing apparatus, at least one additional non-mutable element to the first allocation if the number of mutable elements is greater than the number of non-mutable elements; and
formulating a second allocation of the resources by mutating, based at least in part on a result of the analyzing, comparing, and adding, a resource element of a first type to form a resource element of a second type.
10. The computer readable-medium of claim 9 , wherein the operations further comprise generating the placement by simultaneous dynamical integration of an analogous system of nodes and forces.
11. The computer readable-medium of claim 10 , wherein one or more of the forces are damping, attractive, or spreading forces.
12. A system comprising:
a processor; and
a storage medium coupled to the processor by way of a bus, the storage medium having stored thereon, instructions that, in response to execution by the processor, cause the system to:
analyze a placement of devices of at least a portion of a netlist of an integrated circuit, wherein the placement is in accordance with a first allocation of resources;
compare a number of non-mutable elements of the resources of the first allocation to a number of mutable elements of the resources of the first allocation;
add at least one additional non-mutable element to the first allocation if the number of mutable elements is greater than the number of non-mutable elements; and
formulate a second allocation of the resources by mutating, based at least in part on a result of said analyze, compare, and add, a resource element of a first type to form a resource element of a second type.
13. The system of claim 12 , wherein the non-mutable elements and the mutable elements comprise resource elements of a first type; and
wherein said add comprises mutating resource elements of a second type if the number of mutable elements is greater than the number of non-mutable elements.
14. The system of claim 12 , wherein said compare is performed before said formulate.
15. The system of claim 12 , wherein the devices comprise a first driver, wherein the instructions, in response to execution by the processor, further cause the system to replace the first driver with a second driver, and wherein the first driver and the second driver have different drive strengths.
16. The system of claim 12 , wherein the devices comprise at least one driver, and wherein the instructions, in response to execution by the processor, further cause the system to modify a drive strength of the at least one driver.
17. The system of claim 16 , wherein the instructions, in response to execution by the processor, further causes the system to mutate one or more of the resources to modify the drive strength of the at least one driver.
18. The system of claim 12 , wherein the instructions, in response to execution by the processor, further causes the system to insert a buffer among the devices to modify a timing of the netlist.