Patent Assignment
Reel/Frame 020929/0950
Assignment of Assignor's Interest
Recorded: 2008-05-09
Pages: 7
Assignors
SINGH, BALVINDER
Executed: 2008-04-15
O'RIORDAN, DONALD
Executed: 2008-04-03
ARSINTESCU, BOGDAN GEORGE
Executed: 2008-04-03
GOEL, ALKA
Executed: 2008-04-15
DESHPANDE, DEVENDRA RAMAKANT
Executed: 2008-04-15
Assignee
CADENCE DESIGN SYSTEMS, INC.
2655 SEELY AVENUE. M/S 5B1, SAN JOSE, CALIFORNIA, 95134
Covered Property
(1)
System and Method for Circuit Schematic Generation